使用verilog语言写一个移位寄存器的代码

module shift_register(input clk, input reset, input shift_in, output reg [7:0] shift_out);

reg [7:0] reg;

always @(posedge clk) begin
if (reset) begin
reg <= 8'b00000000;
shift_out <= 8'b00000000;
end else begin
if (shift_in) begin
reg <= {reg[6:0], shift_in};
shift_out <= reg[7];
end else begin
reg <= reg;
shift_out <= reg[7];
end
end
end

endmodule