帮我用Verilog的generate语句写一个输入为16bit数据经过八个D触发器串联的例化语句

module eight_DFFs(
input [15:0] data,
input clk,
output [7:0] Q
);

genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : DFF
DFF dff(
.D(i == 0 ? data : DFF[i-1].Q),
.clk(clk),
.Q(Q[i])
);
end
endgenerate

endmodule

module DFF(
input D,
input clk,
output reg Q
);

always @(posedge clk) begin
Q <= D;
end

endmodule