用verilog HDL 设计十进制加计数器，并有异步清零信号Rd 使能EN计数，cout为计数器进位标志位，并编写测试模块

module decimal_counter (
input clk, // 时钟信号
input rst, // 复位信号
input en, // 使能信号
input rd, // 清零信号
output reg [3:0] count, // 计数器输出
output reg cout // 进位标志位
);

always @(posedge clk, posedge rst) begin
if (rst) begin
count <= 4'b0000;
cout <= 1'b0;
end else if (en) begin
if (count == 4'b1001) begin
count <= 4'b0000;
cout <= 1'b1;
end else begin
count <= count + 1;
cout <= 1'b0;
end
end else if (rd) begin
count <= 4'b0000;
cout <= 1'b0;
end
end

endmodule

module test_decimal_counter;

reg clk, rst, en, rd;
wire [3:0] count;
wire cout;

decimal_counter dut (
.clk(clk),
.rst(rst),
.en(en),
.rd(rd),
.count(count),
.cout(cout)
);

initial begin
clk = 0;
rst = 1;
en = 0;
rd = 0;
#10 rst = 0;
#10 en = 1;
#100 rd = 1;
#10 rd = 0;
#100 en = 0;
#100 en = 1;
#100 en = 0;
#100 $finish;
end

always #5 clk = ~clk;

endmodule