（1）利用40MHz系统时钟，进行时钟分频，产生1Hz时钟信号clk1；（2）8个LED灯每隔1S依次点亮，数码管从1开始计数，直到8结束，依次循环；（3）8个LED灯每隔0.5S隔位点亮（比如1,3,5,7,2,4,6,8），数码管显示具体数字，依次循环；（4）使用Quartus II编写Verilog HDL

以下是Verilog HDL代码：

module clock_divider(
    input clk,
    output reg clk1
    );
    
    reg [25:0] counter;
    
    always @(posedge clk) begin
        if (counter == 40000000 - 1) begin
            counter <= 0;
            clk1 <= ~clk1;
        end else begin
            counter <= counter + 1;
        end
    end
    
endmodule

module led_counter(
    input clk,
    input rst,
    input [3:0] digit,
    output reg [7:0] led
    );
    
    reg [2:0] count;
    reg [2:0] led_count;
    
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            led <= 8'b00000000;
            count <= 3'b000;
            led_count <= 3'b000;
        end else if (count == 3'b000 && led_count == 3'b000) begin
            led <= 8'b00000001;
            count <= count + 1;
        end else if (count == 3'b001) begin
            led <= 8'b00000010;
            count <= count + 1;
        end else if (count == 3'b010) begin
            led <= 8'b00000100;
            count <= count + 1;
        end else if (count == 3'b011) begin
            led <= 8'b00001000;
            count <= 3'b000;
            if (led_count == 3'b111) begin
                led_count <= 3'b000;
            end else begin
                led_count <= led_count + 1;
            end
        end else begin
            count <= count + 1;
        end
    end
    
endmodule

module led_and_digit_counter(
    input clk,
    input rst,
    output reg [7:0] led,
    output reg [3:0] digit
    );
    
    reg [2:0] count;
    reg [2:0] led_count;
    reg [3:0] digit_count;
    
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            led <= 8'b00000000;
            digit <= 4'b0001;
            count <= 3'b000;
            led_count <= 3'b000;
            digit_count <= 4'b0001;
        end else if (count == 3'b000 && led_count == 3'b000) begin
            led <= 8'b01010101;
            count <= count + 1;
        end else if (count == 3'b001) begin
            led <= 8'b10101010;
            count <= count + 1;
        end else if (count == 3'b010) begin
            led <= 8'b01010101;
            count <= 3'b000;
            if (led_count == 3'b111) begin
                led_count <= 3'b000;
            end else begin
                led_count <= led_count + 1;
            end
        end else begin
            count <= count + 1;
        end
        
        if (digit_count == 4'b0001) begin
            digit <= 4'b0001;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0010) begin
            digit <= 4'b0010;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0011) begin
            digit <= 4'b0011;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0100) begin
            digit <= 4'b0100;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0101) begin
            digit <= 4'b0101;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0110) begin
            digit <= 4'b0110;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b0111) begin
            digit <= 4'b0111;
            digit_count <= digit_count + 1;
        end else if (digit_count == 4'b1000) begin
            digit <= 4'b1000;
            digit_count <= 4'b0001;
        end
        
    end
    
endmodule

这个代码分为3个模块：

1. `clock_divider`模块用于将输入的时钟信号`clk`分频为1Hz的信号`clk1`。
2. `led_counter`模块用于每隔1秒依次点亮8个LED灯，并且数码管从1开始计数，直到8结束，依次循环。
3. `led_and_digit_counter`模块用于每隔0.5秒隔位点亮8个LED灯，数码管显示具体数字，依次循环。

需要注意的是，这个代码中使用了时钟分频，因此需要确保分频后的时钟信号`clk1`的时序满足所需的要求。