verilog自动售货机设计

下面是一个简单的 Verilog 自动售货机设计示例：

module vending_machine(clk, reset, coin, cola, sprite, water, dispense);

  parameter IDLE = 2'b00, COIN_INSERTED = 2'b01, DISPENSE = 2'b10;

  input clk, reset, coin, cola, sprite, water;
  output reg dispense;

  reg [1:0] state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      state <= IDLE;
    end else begin
      state <= next_state;
    end
  end

  always @(*) begin
    case(state)
      IDLE: begin
        if (coin) begin
          next_state = COIN_INSERTED;
        end else begin
          next_state = IDLE;
        end
      end
      COIN_INSERTED: begin
        if (cola) begin
          next_state = DISPENSE;
        end else if (sprite) begin
          next_state = DISPENSE;
        end else if (water) begin
          next_state = DISPENSE;
        end else begin
          next_state = COIN_INSERTED;
        end
      end
      DISPENSE: begin
        dispense = 1;
        next_state = IDLE;
      end
    endcase
  end
endmodule

该自动售货机有三个状态，分别是 IDLE、COIN_INSERTED 和 DISPENSE。当硬币被投入时，自动售货机进入 COIN_INSERTED 状态。在这个状态下，如果选择了可乐、雪碧或者水，自动售货机将进入 DISPENSE 状态并出货。如果没有选择，则继续保持 COIN_INSERTED 状态。在 DISPENSE 状态下，自动售货机会出货并回到 IDLE 状态。