adc_vol {}adc:ch0 = 475.854919mV python 怎么把等号后的数字拿出来
时间: 2023-06-01 09:05:57 浏览: 60
你可以使用正则表达式或字符串切片来提取等号后的数字,例如可以使用以下代码来获取 "475.854919":
```
import re
str = "adc_vol {}adc:ch0 = 475.854919mV"
result = re.search("= ([0-9.]+)mV", str)
if result:
print(result.group(1))
```
或者可以使用以下代码:
```
str = "adc_vol {}adc:ch0 = 475.854919mV"
num_str = str.split('=')[1].split('mV')[0].strip()
print(num_str)
```
相关问题
这两个Verilog代码可以放在一个.v文件中吗:1.`timescale 1ns / 1ps module Top(clk,sw,led,flag, ADC_sdata, ADC_sclk,ADC_csn,slec_wei,slec_duan); input clk; input [3:0]sw; output reg [7:0] led; input flag; input ADC_sdata; output ADC_sclk,ADC_csn; output [7:0] slec_wei; output [7:0] slec_duan; wire [11:0] adc_res; wire adc_valid; wire [19:0]cout; always@(posedge clk)if(adc_valid) led<=adc_res[11:4]; PmodAD1 U0( .clk(clk), .rst(1’b0), .ADC_sdata(ADC_sdata), .ADC_sclk(ADC_sclk), .ADC_csn(ADC_csn), .adc_res(adc_res), .adc_valid(adc_valid) ); data_ad_pro U1( .sys_clk(clk), .rst_n(1’b1), .pre_data(adc_res[11:4]), .cout(cout) ); display U2( .sys_clk(clk), .rst_n(1’b1), .cout(cout), .sw(sw), .flag(flag), .slec_wei(slec_wei), .slec_duan(slec_duan) ); endmodule ———————2.module PmodAD1( clk,rst, ADC_sdata,ADC_sclk,ADC_csn,adc_res,adc_valid); input clk,rst, ADC_sdata; output reg ADC_sclk,ADC_csn; output reg [11:0] adc_res; output reg adc_valid; reg [7:0] cntr; always@(posedge clk) if(rst)cntr<=0;else if(cntr==34)cntr<=0;else cntr<=cntr+1; always@(posedge clk) case (cntr) 0: ADC_csn<=0; 33: ADC_csn<=1; endcase always@(posedge clk) case(cntr) 34,0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,33:ADC_sclk<=1; default ADC_sclk<=0; endcase always@(posedge clk) case(cntr) 8: adc_res[11]<= ADC_sdata; 10:adc_res[10]<= ADC_sdata; 12:adc_res[9]<= ADC_sdata; 14:adc_res[8]<= ADC_sdata; 16:adc_res[7]<= ADC_sdata; 18:adc_res[6]<= ADC_sdata; 20:adc_res[5]<= ADC_sdata; 22:adc_res[4]<= ADC_sdata; 24:adc_res[3]<= ADC_sdata; 26:adc_res[2]<= ADC_sdata; 28:adc_res[1]<= ADC_sdata; 30:adc_res[0]<= ADC_sdata; endcase always@(posedge clk)adc_valid<=cntr==32; endmodule
可以将两个模块放在同一个文件中,但需要注意的是,需要在两个模块之间添加一个模块分割符`//----`,否则会报错。同时,建议将两个模块中的端口名进行修改,以免出现冲突。下面是修改后的代码示例:
```
//----Top module----
`timescale 1ns / 1ps
module Top(
input clk,
input [3:0] sw,
output reg [7:0] led,
input flag,
input ADC_sdata,
output ADC_sclk,
output ADC_csn,
output [7:0] slec_wei,
output [7:0] slec_duan
);
wire [11:0] adc_res;
wire adc_valid;
wire [19:0] cout;
always@(posedge clk)
if(adc_valid)
led <= adc_res[11:4];
PmodAD1 U0(
.clk(clk),
.rst(1'b0),
.ADC_sdata(ADC_sdata),
.ADC_sclk(ADC_sclk),
.ADC_csn(ADC_csn),
.adc_res(adc_res),
.adc_valid(adc_valid)
);
data_ad_pro U1(
.sys_clk(clk),
.rst_n(1'b1),
.pre_data(adc_res[11:4]),
.cout(cout)
);
display U2(
.sys_clk(clk),
.rst_n(1'b1),
.cout(cout),
.sw(sw),
.flag(flag),
.slec_wei(slec_wei),
.slec_duan(slec_duan)
);
endmodule
//----PmodAD1 module----
module PmodAD1(
input clk,
input rst,
input ADC_sdata,
output reg ADC_sclk,
output reg ADC_csn,
output reg [11:0] adc_res,
output reg adc_valid
);
reg [7:0] cntr;
always@(posedge clk)
if(rst)
cntr <= 0;
else if(cntr == 34)
cntr <= 0;
else
cntr <= cntr + 1;
always@(posedge clk)
case(cntr)
0: ADC_csn <= 0;
33: ADC_csn <= 1;
endcase
always@(posedge clk)
case(cntr)
34, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 33: ADC_sclk <= 1;
default ADC_sclk <= 0;
endcase
always@(posedge clk)
case(cntr)
8: adc_res[11] <= ADC_sdata;
10: adc_res[10] <= ADC_sdata;
12: adc_res[9] <= ADC_sdata;
14: adc_res[8] <= ADC_sdata;
16: adc_res[7] <= ADC_sdata;
18: adc_res[6] <= ADC_sdata;
20: adc_res[5] <= ADC_sdata;
22: adc_res[4] <= ADC_sdata;
24: adc_res[3] <= ADC_sdata;
26: adc_res[2] <= ADC_sdata;
28: adc_res[1] <= ADC_sdata;
30: adc_res[0] <= ADC_sdata;
endcase
always@(posedge clk)
adc_valid <= cntr == 32;
endmodule
```
解释以下代码 ADC_InitStructure.ADC_ContinuousConvMode=ENABLE; ADC_InitStructure.ADC_DataAlign=ADC_DataAlign_Right; ADC_InitStructure.ADC_ExternalTrigConv=ADC_ExternalTrigConv_None; ADC_InitStructure.ADC_Mode=ADC_Mode_Independent; ADC_InitStructure.ADC_NbrOfChannel=1; ADC_InitStructure.ADC_ScanConvMode=DISABLE; ADC_Init(ADC1,&ADC_InitStructure); ADC_Cmd(ADC1,ENABLE); ADC_ResetCalibration(ADC1); while(ADC_GetResetCalibrationStatus(ADC1)); ADC_StartCalibration(ADC1); while(ADC_GetCalibrationStatus(ADC1));
这段代码是在配置STM32的ADC模块,具体解释如下:
```
ADC_InitStructure.ADC_ContinuousConvMode=ENABLE; // 连续转换模式
ADC_InitStructure.ADC_DataAlign=ADC_DataAlign_Right; // 数据右对齐
ADC_InitStructure.ADC_ExternalTrigConv=ADC_ExternalTrigConv_None; // 外部触发转换禁止
ADC_InitStructure.ADC_Mode=ADC_Mode_Independent; // 独立模式
ADC_InitStructure.ADC_NbrOfChannel=1; // 要转换的通道数
ADC_InitStructure.ADC_ScanConvMode=DISABLE; // 扫描模式禁止
ADC_Init(ADC1,&ADC_InitStructure); // 初始化ADC1
ADC_Cmd(ADC1,ENABLE); // 使能ADC1
ADC_ResetCalibration(ADC1); // 复位ADC1的校准寄存器
while(ADC_GetResetCalibrationStatus(ADC1)); // 等待ADC1的校准寄存器复位完成
ADC_StartCalibration(ADC1); // 开始ADC1的校准
while(ADC_GetCalibrationStatus(ADC1)); // 等待ADC1的校准完成
```
这段代码中,首先通过结构体`ADC_InitStructure`来对ADC模块进行配置,然后调用`ADC_Init()`函数对ADC进行初始化。接下来,使能ADC模块,复位ADC模块的校准寄存器,等待复位完成,启动校准,等待校准完成。这样就完成了对ADC模块的初始化和校准,可以进行转换操作了。