8-3线优先编码器vhdl

以下是一个简单的8-3线优先编码器的VHDL代码：

entity priority_encoder is
    port (
        inputs: in std_logic_vector(7 downto 0);
        output: out std_logic_vector(2 downto 0)
    );
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
    process(inputs)
    begin
        case inputs is
            when "00000001" => output <= "000";
            when "00000010" => output <= "001";
            when "00000100" => output <= "010";
            when "00001000" => output <= "011";
            when "00010000" => output <= "100";
            when "00100000" => output <= "101";
            when "01000000" => output <= "110";
            when "10000000" => output <= "111";
            when others => output <= "000";
        end case;
    end process;
end Behavioral;

这个编码器将8个输入位编码为3个输出位。输入位中的每个位都有一个优先级，如果多个位都是1，则具有最高优先级的位将被编码。输出位是一个3位的二进制数，表示具有最高优先级的输入位。