用Verilog写一个以0xFF为头包，接收4个字节，然后再以相同的顺序发送，先发0x55，数据放在IO口上的代码

module sender_and_receiver(
input clk, // 时钟信号
input rst_n, // 复位信号，低有效
input [7:0] in_data, // 输入数据
output reg [7:0] out_data, // 输出数据
output reg out_vld // 输出数据有效信号
);

reg [1:0] state;
reg [7:0] reg_data;
reg [3:0] cnt;
assign out_data = cnt > 1 ? reg_data : 8'b01010101;

always @(posedge clk, negedge rst_n)
begin
if (~rst_n) begin
state <= 2'b00;
cnt <= 0;
out_vld <= 1'b0;
end
else begin
case (state)
2'b00:
begin
reg_data <= 0;
cnt <= 0;
out_vld <= 1'b0;

if (in_data == 8'hFF)
state <= 2'b01;
end

2'b01:
begin
reg_data[cnt * 8 +: 8] <= in_data;
cnt <= cnt + 1;

if (cnt == 3)
state <= 2'b10;
end

2'b10:
begin
if (out_vld && cnt == 0)
state <= 2'b00;
else if (~out_vld && cnt == 0)
state <= 2'b11;

if (cnt == 3) begin
out_vld <= 1'b1;
reg_data <= 0;
cnt <= 0;
end
end

2'b11:
begin
if (out_vld && cnt == 0)
state <= 2'b00;
else if (~out_vld && cnt == 0)
state <= 2'b10;

if (cnt == 0)
out_vld <= 1'b0;
end
endcase
end
end

endmodule