1.用VHDL写出在DISP7-DISP3数码管上显示班级和班内序号 2. 设计并生成一个随机数生成电路，每两秒生成一个0~999之间的随机数，并且在数码管DISP2-DISP0上显示生成的随机数。 3. 为系统设置一个复位键，复位后数码管DISP2~DISP0上显示”000”,2秒后生成并且显示随机数，并且使用复位键进行复位，

1. VHDL 代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Display is
    port (
        class : in std_logic_vector(3 downto 0);
        number : in std_logic_vector(3 downto 0);
        clk : in std_logic;
        reset : in std_logic;
        disp : out std_logic_vector(6 downto 0)
    );
end entity;

architecture Behavior of Display is
    signal cnt : integer range 0 to 100000000 := 0;
    signal class_num : integer range 0 to 99 := 0;
    signal number_num : integer range 0 to 99 := 0;
    signal disp_num : integer range 0 to 999 := 0;
begin
    process (clk, reset)
    begin
        if reset = '1' then
            cnt <= 0;
            class_num <= 0;
            number_num <= 0;
            disp_num <= 0;
            disp <= "0000000";
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
            if cnt = 10000000 then -- 每10秒更新一次显示
                cnt <= 0;
                class_num <= to_integer(unsigned(class));
                number_num <= to_integer(unsigned(number));
                disp_num <= class_num * 100 + number_num;
            end if;
        end if;
    end process;

    process (disp_num)
    begin
        case disp_num is
            when 0 =>
                disp <= "1000000"; -- 0
            when 1 =>
                disp <= "1111001"; -- 1
            when 2 =>
                disp <= "0100100"; -- 2
            when 3 =>
                disp <= "0110000"; -- 3
            when 4 =>
                disp <= "0011001"; -- 4
            when 5 =>
                disp <= "0010010"; -- 5
            when 6 =>
                disp <= "0000010"; -- 6
            when 7 =>
                disp <= "1111000"; -- 7
            when 8 =>
                disp <= "0000000"; -- 8
            when 9 =>
                disp <= "0010000"; -- 9
            when 10 =>
                disp <= "0001000"; -- A
            when 11 =>
                disp <= "0000011"; -- b
            when 12 =>
                disp <= "0100111"; -- C
            when 13 =>
                disp <= "0100010"; -- d
            when 14 =>
                disp <= "0000110"; -- E
            when 15 =>
                disp <= "0001110"; -- F
            when others =>
                disp <= "1111111"; -- 空白
        end case;
    end process;
end architecture;

2. VHDL 代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RandomGenerator is
    port (
        clk : in std_logic;
        reset : in std_logic;
        random_num : out std_logic_vector(9 downto 0);
        disp : out std_logic_vector(6 downto 0)
    );
end entity;

architecture Behavior of RandomGenerator is
    signal cnt : integer range 0 to 100000000 := 0;
    signal rand : integer range 0 to 999 := 0;
begin
    process (clk, reset)
    begin
        if reset = '1' then
            cnt <= 0;
            rand <= 0;
            random_num <= "0000000000";
            disp <= "0000000";
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
            if cnt = 20000000 then -- 每2秒更新一次随机数
                cnt <= 0;
                rand <= integer(unsigned(to_unsigned(rand, 10))) + 1;
                if rand >= 1000 then
                    rand <= 0;
                end if;
                random_num <= std_logic_vector(to_unsigned(rand, 10));
            end if;
        end if;
    end process;

    process (random_num)
    begin
        case random_num is
            when "0000" =>
                disp <= "1000000"; -- 0
            when "0001" =>
                disp <= "1111001"; -- 1
            when "0010" =>
                disp <= "0100100"; -- 2
            when "0011" =>
                disp <= "0110000"; -- 3
            when "0100" =>
                disp <= "0011001"; -- 4
            when "0101" =>
                disp <= "0010010"; -- 5
            when "0110" =>
                disp <= "0000010"; -- 6
            when "0111" =>
                disp <= "1111000"; -- 7
            when "1000" =>
                disp <= "0000000"; -- 8
            when "1001" =>
                disp <= "0010000"; -- 9
            when others =>
                disp <= "1111111"; -- 空白
        end case;
    end process;
end architecture;

3. VHDL 代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity DisplayAndGenerator is
    port (
        class : in std_logic_vector(3 downto 0);
        number : in std_logic_vector(3 downto 0);
        clk : in std_logic;
        reset : in std_logic;
        random_num : out std_logic_vector(9 downto 0);
        disp : out std_logic_vector(6 downto 0)
    );
end entity;

architecture Behavior of DisplayAndGenerator is
    signal cnt : integer range 0 to 100000000 := 0;
    signal class_num : integer range 0 to 99 := 0;
    signal number_num : integer range 0 to 99 := 0;
    signal disp_num : integer range 0 to 999 := 0;
    signal rand : integer range 0 to 999 := 0;
begin
    process (clk, reset)
    begin
        if reset = '1' then
            cnt <= 0;
            class_num <= 0;
            number_num <= 0;
            disp_num <= 0;
            rand <= 0;
            random_num <= "0000000000";
            disp <= "0000000";
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
            if cnt = 20000000 then -- 每2秒更新一次随机数
                cnt <= 0;
                rand <= integer(unsigned(to_unsigned(rand, 10))) + 1;
                if rand >= 1000 then
                    rand <= 0;
                end if;
                random_num <= std_logic_vector(to_unsigned(rand, 10));
            end if;
            if cnt = 10000000 then -- 每10秒更新一次显示
                class_num <= to_integer(unsigned(class));
                number_num <= to_integer(unsigned(number));
                disp_num <= class_num * 100 + number_num;
            end if;
        end if;
    end process;

    process (disp_num)
    begin
        case disp_num is
            when 0 =>
                disp <= "1000000"; -- 0
            when 1 =>
                disp <= "1111001"; -- 1
            when 2 =>
                disp <= "0100100"; -- 2
            when 3 =>
                disp <= "0110000"; -- 3
            when 4 =>
                disp <= "0011001"; -- 4
            when 5 =>
                disp <= "0010010"; -- 5
            when 6 =>
                disp <= "0000010"; -- 6
            when 7 =>
                disp <= "1111000"; -- 7
            when 8 =>
                disp <= "0000000"; -- 8
            when 9 =>
                disp <= "0010000"; -- 9
            when 10 =>
                disp <= "0001000"; -- A
            when 11 =>
                disp <= "0000011"; -- b
            when 12 =>
                disp <= "0100111"; -- C
            when 13 =>
                disp <= "0100010"; -- d
            when 14 =>
                disp <= "0000110"; -- E
            when 15 =>
                disp <= "0001110"; -- F
            when others =>
                disp <= "1111111"; -- 空白
        end case;
    end process;
end architecture;