过撰写 Verilog HDL 代码设计实现 60 进制和 24 进制的循环计数

以下是 Verilog HDL 代码实现 60 进制和 24 进制的循环计数器：

60 进制计数器：

module counter_60(
    input clk,
    input rst,
    output reg [5:0] sec,
    output reg [5:0] min,
    output reg [4:0] hour
);

always @(posedge clk or posedge rst) begin
    if (rst) begin
        sec <= 6'b0;
        min <= 6'b0;
        hour <= 5'b0;
    end else begin
        if (sec == 6'd59) begin
            sec <= 6'b0;
            if (min == 6'd59) begin
                min <= 6'b0;
                if (hour == 5'd23) begin
                    hour <= 5'b0;
                end else begin
                    hour <= hour + 5'd1;
                end
            end else begin
                min <= min + 6'd1;
            end
        end else begin
            sec <= sec + 6'd1;
        end
    end
end

endmodule

24 进制计数器：

module counter_24(
    input clk,
    input rst,
    output reg [5:0] sec,
    output reg [5:0] min,
    output reg [4:0] hour
);

always @(posedge clk or posedge rst) begin
    if (rst) begin
        sec <= 6'b0;
        min <= 6'b0;
        hour <= 5'b0;
    end else begin
        if (sec == 6'd59) begin
            sec <= 6'b0;
            if (min == 6'd59) begin
                min <= 6'b0;
                if (hour == 5'd23) begin
                    hour <= 5'b0;
                end else begin
                    hour <= hour + 5'd1;
                end
            end else begin
                min <= min + 6'd1;
            end
        end else begin
            sec <= sec + 6'd1;
        end
    end
end

endmodule