always @ (posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) seg_led <= 8'b0; else begin case (num) 4'd0 : seg_led <= 8'b1100_0000; 4'd1 : seg_led <= 8'b1111_1001; 4'd2 : seg_led <= 8'b1010_0100; 4'd3 : seg_led <= 8'b1011_0000; 4'd4 : seg_led <= 8'b1001_1001; 4'd5 : seg_led <= 8'b1001_0010; 4'd6 : seg_led <= 8'b1000_0010; 4'd7 : seg_led <= 8'b1111_1000; 4'd8 : seg_led <= 8'b1000_0000; 4'd9 : seg_led <= 8'b1001_0000; default : seg_led <= 8'b1100_0000; endcase end end

这段代码也是一个Verilog HDL中的always块，它在时钟上升沿或复位信号下降沿时执行。如果复位信号为低电平，数码管的输出信号seg_led将被赋值为8'b0。否则，根据数字信号num的值执行不同的case分支，将相应的数码管的控制信号输出到seg_led信号中。具体来说，当num为0时，seg_led输出1100_0000；当num为1时，seg_led输出1111_1001；当num为2时，seg_led输出1010_0100；当num为3时，seg_led输出1011_0000；当num为4时，seg_led输出1001_1001；当num为5时，seg_led输出1001_0010；当num为6时，seg_led输出1000_0010；当num为7时，seg_led输出1111_1000；当num为8时，seg_led输出1000_0000；当num为9时，seg_led输出1001_0000。如果num的值不在0到9之间，seg_led将被赋值为1100_0000。

相关问题

module ram_write ( input wire sys_clk , input wire sys_rst_n , input wire cnt_rcd, input wire [7:0] seg_cnt_data0 , input wire [7:0] seg_cnt_data1 , input wire [7:0] seg_cnt_data2 , input wire [7:0] seg_cnt_data3 , input wire [7:0] seg_cnt_data4 , input wire [7:0] seg_cnt_data5 , output reg [4:0] addr, output reg write_en , output reg [7:0] data_in ); reg [3:0] bite ; reg [3:0] times=0; always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin write_en <= 1'b0 ; end else if (cnt_rcd) begin write_en <= 1'b1; times <= times + 1; end else begin write_en <= 1'b0; end end always @(posedge sys_clk or negedge sys_rst_n) if(!sys_rst_n) begin bite <='d0; addr <='d0; data_in <='d0; end else if(write_en) begin case(bite) 'd0: begin addr <= 2'd0+6times ; data_in<= seg_cnt_data0 ; bite<=bite + 1 ; end 'd1: begin addr <= 2'd1+6times ; data_in<= seg_cnt_data1; bite<=bite + 1 ; end 'd2: begin addr <= 2'd2+6times ; data_in<= seg_cnt_data2 ; bite<=bite + 1 ; end 'd3: begin addr <= 2'd3+6times ; data_in<= seg_cnt_data3 ; bite<=bite + 1 ; end 'd4: begin addr <= 2'd4+6times ; data_in<= seg_cnt_data4 ; bite<=bite + 1 ; end 'd5: begin addr <= 2'd5+6times ; data_in<= seg_cnt_data5 ; bite<=bite + 1 ; end default: ; endcase end endmodule修改代码

根据您提供的代码，我发现在更新 `addr` 时，使用的是 `6times`，这里应该是 `6*times`，需要在乘法符号前面加上 `*`，以正确计算地址。请尝试修改如下代码：

module ram_write (
    input wire sys_clk,
    input wire sys_rst_n,
    input wire cnt_rcd,
    input wire [7:0] seg_cnt_data0,
    input wire [7:0] seg_cnt_data1,
    input wire [7:0] seg_cnt_data2,
    input wire [7:0] seg_cnt_data3,
    input wire [7:0] seg_cnt_data4,
    input wire [7:0] seg_cnt_data5,
    output reg [4:0] addr,
    output reg write_en,
    output reg [7:0] data_in
);

    reg [3:0] bite;
    reg [3:0] times = 0;

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            write_en <= 1'b0;
        end else if (cnt_rcd) begin
            write_en <= 1'b1;
            times <= times + 1;
        end else begin
            write_en <= 1'b0;
        end
    end

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            bite <= 'd0;
            addr <= 'd0;
            data_in <= 'd0;
        end else if (write_en) begin
            case (bite)
                'd0: begin
                    addr <= 2'd0 + 6 * times;
                    data_in <= seg_cnt_data0;
                    bite <= bite + 1;
                end
                'd1: begin
                    addr <= 2'd1 + 6 * times;
                    data_in <= seg_cnt_data1;
                    bite <= bite + 1;
                end
                'd2: begin
                    addr <= 2'd2 + 6 * times;
                    data_in <= seg_cnt_data2;
                    bite <= bite + 1;
                end
                'd3: begin
                    addr <= 2'd3 + 6 * times;
                    data_in <= seg_cnt_data3;
                    bite <= bite + 1;
                end
                'd4: begin
                    addr <= 2'd4 + 6 * times;
                    data_in <= seg_cnt_data4;
                    bite <= bite + 1;
                end
                'd5: begin
                    addr <= 2'd5 + 6 * times;
                    data_in <= seg_cnt_data5;
                    bite <= bite + 1;
                end
                default: ;
            endcase
        end
    end

endmodule

请尝试使用上述代码，看看问题是否得到解决。

module project( clk, rst, ENA, init_num, SEL, SEG ); input clk; input rst; input ENA; input [3:0]init_num; output [1:0]SEL; output [7:0]SEG; reg clk_1Hz; reg [27:0]div_cnt; always@(posedge clk or negedge rst) if (!rst) div_cnt <= 0; else if (div_cnt >= 28'd99999999) // 1Hz——99999999 div_cnt <= 0; else div_cnt <= div_cnt + 1'b1; always@(posedge clk or negedge rst) if (!rst) clk_1Hz <= 0; else if (div_cnt == 28'd99999999) // 1Hz--99999999 clk_1Hz <= 1'b1; else clk_1Hz <= 0; reg [3:0]disp_num = 0; reg reverse = 0; always@(posedge clk_1Hz or negedge rst) begin if (!rst) disp_num <= init_num; else if (!ENA) ; else if (disp_num == 15) begin //正向计数到15 reverse <= 1; disp_num <= disp_num - 1; end else if (disp_num == 0 && reverse) begin //反向计数到0 reverse <= 0; disp_num <= disp_num + 1; end else if (!reverse) disp_num <= disp_num + 1; else if (reverse) disp_num <= disp_num - 1; end smg_disp_1 u1( .Clk(clk), .Reset_n(rst), .Disp_Data(disp_num), .SEL(SEL), .SEG(SEG) ); endmodule给代码进行注释

下面是代码的注释：

module project(
    clk,    //时钟信号
    rst,    //同步复位信号
    ENA,    //使能控制信号
    init_num,   //预置数
    SEL,    //数码管位选信号
    SEG     //数码管段选信号
);
    input clk;  //时钟信号
    input rst;  //同步复位信号
    input ENA;  //使能控制信号
    input [3:0] init_num;   //预置数，4位二进制数
    output [1:0] SEL;  //数码管位选信号
    output [7:0] SEG;  //数码管段选信号

    reg clk_1Hz;   //1Hz的时钟信号
    reg [27:0] div_cnt; //时钟信号的分频计数器

    always@(posedge clk or negedge rst)   //时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            div_cnt <= 0;   //分频计数器清零
        else if (div_cnt >= 28'd99999999) //分频计数器计数到99999999
            div_cnt <= 0;   //分频计数器清零
        else
            div_cnt <= div_cnt + 1'b1;   //分频计数器加1

    always@(posedge clk or negedge rst)   //时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            clk_1Hz <= 0;   //1Hz的时钟信号为低电平
        else if (div_cnt == 28'd99999999) //分频计数器计数到99999999
            clk_1Hz <= 1'b1;    //1Hz的时钟信号为高电平
        else
            clk_1Hz <= 0;   //1Hz的时钟信号为低电平

    reg [3:0] disp_num = 0; //计数器的输出数值，默认为0
    reg reverse = 0;    //计数器的计数方向，默认为正向计数

    always@(posedge clk_1Hz or negedge rst) begin   //1Hz的时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            disp_num <= init_num;   //计数器的输出数值为预置数
        else if (!ENA) //使能控制信号为低电平
            ;   //计数器不进行计数
        else if (disp_num == 15) begin   //正向计数到15
            reverse <= 1;   //计数方向反转
            disp_num <= disp_num - 1;   //计数器减1
        end
        else if (disp_num == 0 && reverse) begin //反向计数到0
            reverse <= 0;   //计数方向反转
            disp_num <= disp_num + 1;   //计数器加1
        end
        else if (!reverse) //正向计数
            disp_num <= disp_num + 1;   //计数器加1
        else if (reverse)  //反向计数
            disp_num <= disp_num - 1;   //计数器减1
    end

    smg_disp_1 u1(  //数码管驱动模块
        .Clk(clk), //时钟信号
        .Reset_n(rst),  //同步复位信号
        .Disp_Data(disp_num),   //计数器的输出数值
        .SEL(SEL),  //数码管位选信号
        .SEG(SEG)   //数码管段选信号
    );
endmodule