VHDL设计指南（第三版）：从入门到案例详解

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《设计者指南：VHDL（第三版）》是一本国外的经典教材，专为数字电子系统设计师提供指导。该书由前后连贯的章节构成，按照逐步深入的方式组织，每个章节在介绍新概念或语言特性时，都伴随着实例演示，便于理解和掌握。书中贯穿三个案例研究，将前面章节的内容以扩展的工作示例形式整合，帮助读者将理论知识应用于实际设计。 VHDL全称为Very High Speed Integrated Circuit Hardware Description Language，它源于美国政府的VHSIC（Very High Speed Integrated Circuit）计划。该计划的目标是发展一种标准语言来描述集成电路（ICs）的结构和功能，因此VHDL应运而生。最初的标准版本，即VHDL-87，是在1987年由IEEE采纳的，作为IEEE 1076标准，VHDL语言参考手册。随着时间的推移，VHDL标准经历了多次修订。1987年标准发布后，用户对其进行了反馈和建议的分析，这促使IEEE在1992年提出了一次修订版本，即VHDL-93。随后，1998年开始了第二次修订过程，最终在2001年完成，形成了VHDL-2002。此后，VHDL的后续发展并未止步，反映了对语言持续改进和适应现代电子设计需求的决心。本书不仅介绍了VHDL语言的基本原理，还涵盖了从VHDL-87到VHDL-2002的标准演变，包括语法、数据类型、结构化设计元素（如进程、组合逻辑、架构、包和库）、以及设计验证等核心概念。对于FPGA（Field-Programmable Gate Array）的设计者来说，理解并熟练运用VHDL至关重要，因为它提供了描述和实现数字电路行为的通用工具，适用于硬件描述和仿真，是现代硬件开发不可或缺的一部分。通过《设计者指南：VHDL（第三版）》，读者可以系统地学习如何使用VHDL进行硬件描述，包括设计流程、最佳实践和调试技巧，这对于从事数字电路设计、系统集成和验证的专业人士来说，无疑是一本极具价值的参考资料。无论是初学者还是经验丰富的设计师，这本书都能为其提供实用的知识和技能提升。

1.4 VHDL Modeling Concepts 9

modeling languages, the signal assignment statement. This is similar to variable assign-

ment, except that it causes the value on a signal to be updated at some future time.

EXAMPLE 1.2 Behavioral architecture for the four-bit register

To illustrate these ideas, let us look at a behavioral architecture body for the

reg4 en-

tity of Example 1.1:

architecture behav of reg4 is

begin

storage : process is

variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;

begin

wait until clk;

if en then

stored_d0 := d0;

stored_d1 := d1;

stored_d2 := d2;

stored_d3 := d3;

end if;

q0 <= stored_d0 after 5 ns;

q1 <= stored_d1 after 5 ns;

q2 <= stored_d2 after 5 ns;

q3 <= stored_d3 after 5 ns;

end process storage;

end architecture behav;

In this architecture body, the part after the first begin keyword includes one process

statement, which describes how the register behaves. It starts with the process name,

storage, and finishes with the keywords end process.

The process statement defines a sequence of actions that are to take place when

the system is simulated. These actions control how the values on the entity’s ports

change over time; that is, they control the behavior of the entity. This process can

modify the values of the entity’s ports using signal assignment statements.

The way this process works is as follows. When the simulation is started, the sig-

nal values are set to ‘0’, and the process is activated. The process’s variables (listed

after the keyword

variable) are initialized to ‘0’, then the statements are executed in

order. The first statement is a wait statement that causes the process to suspend, that

is, to become inactive. It stays suspended until one of the signals to which it is sensi-

tive changes value. In this case, the process is sensitive only to the signal

clk, since

that is the only one named in the wait statement. When that signal changes value, the

process is resumed and continues executing statements. The next statement is a con-

dition that tests whether the value of the

en signal is ‘1’. If it is, the statements between

the keywords

then and end if are executed, updating the process’s variables using

the values on the input signals. After the conditional if statement, there are four signal

assignment statements that cause the output signals to be updated 5 ns later.

12 Chapter 1 — Fundamental Concepts

gate : entity work.and2(basic)

port map (en, clk, int_clk);

end architecture struct;

The signal declaration, before the keyword begin, defines the internal signals of

the architecture. In this example, the signal

int_clk is declared to carry a bit value (‘0’

or ‘1’). In general, VHDL signals can be declared to carry arbitrarily complex values.

Within the architecture body the ports of the entity are also treated as signals.

In the second part of the architecture body, a number of component instances are

created, representing the subsystems from which the

reg4 entity is composed. Each

component instance is a copy of the entity representing the subsystem, using the cor-

responding

basic architecture body. (The name work refers to the current working

library, in which all of the entity and architecture body descriptions are assumed to

be held.)

The port map specifies the connection of the ports of each component instance

to signals within the enclosing architecture body. For example,

bit0, an instance of

the

d_ff entity, has its port d connected to the signal d0, its port clk connected to the

signal int_clk and its port q connected to the signal q0.

1.4.3 Mixed Structural and Behavioral Models

Models need not be purely structural or purely behavioral. Often it is useful to specify a

model with some parts composed of interconnected component instances, and other parts

described using processes. We use signals as the means of joining component instances

and processes. A signal can be associated with a port of a component instance and can

also be assigned to or read in a process.

We can write such a hybrid model by including both component instance and process

statements in the body of an architecture. These statements are collectively called concur-

rent statements, since the corresponding processes all execute concurrently when the

model is simulated.

EXAMPLE 1.4 A mixed structural and behavioral model for a multiplier

A sequential multiplier consists of a data path and a control section. An outline of a

mixed structural and behavioral model for the multiplier is:

entity multiplier is

port ( clk, reset : in bit;

multiplicand, multiplier : in integer;

product : out integer );

end entity multiplier;

--------------------------------------------------

architecture mixed of multiplier is

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VHDL设计指南（第三版）：从入门到案例详解

VHDL(pdf课件)

VHDL语法入门.pdf

VHDL官方参考手册（1076-2008）.pdf

USE IEEE.STD_LOGIC_1164.ALL

bin_num <= std_logic_vector(to_unsigned(to_integer(numeric_std.unsigned(hex_num)), 16));为何以上代码出现如下错误Error (10482): VHDL error at num_display.vhd(42): object "numeric_std" is used but not declared

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