10
bq24296
,
bq24297
SLUSBP6C – SEPTEMBER 2013 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: bq24296 bq24297
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Electrical Characteristics (continued)
V
VBUS_UVLOZ
< V
VBUS
< V
ACOV
and V
VBUS
> V
BAT
+ V
SLEEP
, T
J
= –40°C to 125°C and T
J
= 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBCOLD1
Cold temperature threshold 1, TS pin
voltage rising threshold
As percentage to V
REGN
REG02[1] = 1
(Approx. -20°C w/ 103AT)
78.5% 79% 79.5%
VBCOLD1_HYS
As percentage to V
REGN
REG02[1] = 1
(Approx. 1°C w/ 103AT)
1%
VBHOT0
Hot temperature threshold, TS pin voltage
falling threshold
As percentage to V
REGN
REG06[3:2] = 01
(Approx. 55°C w/ 103AT)
35.5% 36% 36.5%
VBHOT0_HYS
As percentage to V
REGN
REG06[3:2] = 01
(Approx. 3°C w/ 103AT)
3%
VBHOT1
Hot temperature threshold 1, TS pin
voltage falling threshold
As percentage to V
REGN
REG06[3:2] = 00
(Approx. 60°C w/ 103AT)
32.5% 33% 33.5%
VBHOT1_HYS
As percentage to V
REGN
REG06[3:2] = 00
(Approx. 3°C w/ 103AT)
3%
VBHOT2
Hot temperature threshold 2, TS pin
voltage falling threshold
As percentage to V
REGN
REG06[3:2] = 10
(Approx. 65°C w/ 103AT)
29.5% 30% 30.5%
VBHOT2_HYS
As percentage to V
REGN
REG06[3:2] = 10
(Approx. 3°C w/ 103AT)
3%
CHARGE OVER-CURRENT COMPARATOR
I
HSFET_OCP
HSFET cycle by cycle over-current
threshold
5.3 7.5 A
I
BATFET_OCP
System over load threshold 5.5 6.6 A
V
LSFET_UCP
LSFET charge under-current falling
threshold
From sync mode to non-sync mode 100 mA
F
SW
PWM Switching frequency, and digital
clock
1300 1500 1700 kHz
D
MAX
Maximum PWM duty cycle 97%
V
BTST_REFRESH
Bootstrap refresh comparator threshold
VBTST-VSW when LSFET refresh pulse is requested,
VBUS = 5 V
3.6 V
BOOST MODE OPERATION
V
OTG_REG_ACC
OTG output voltage I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) 5 V
V
OTG_REG_ACC
OTG output voltage accuracy I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) -3% 3%
V
OTG_BAT
Battery voltage exiting OTG mode BAT falling, REG04[1] = 1 2.9 V
I
OTG
OTG mode output current
REG01[0] = 0 1 A
REG01[0] = 1 1.5 A
V
OTG_OVP
OTG over-voltage threshold Rising threshold 5.8 6 V
V
OTG_OVP_HYS
OTG over-voltage threshold hysteresis Falling threshold 300 mV
I
OTG_LSOCP
LSFET cycle by cycle current limit 5 A
I
OTG_HSZCP
HSFET under current falling threshold 100 mA
I
RBFET_OCP
RBFET over-current threshold
REG01[0] = 0 1.00 1.15 1.30
A
REG01[0] = 1 1.50 1.70 1.90
REGN LDO
V
REGN
REGN LDO output voltage
V
VBUS
= 6 V, I
REGN
= 40 mA 4.8 5 5.5 V
V
VBUS
= 5 V, I
REGN
= 20 mA 4.7 4.8 V
I
REGN
REGN LDO current limit V
VBUS
= 5 V, V
REGN
= 3.8 V 50 mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)
V
ILO
Input low threshold 0.4 V
V
IH
Input high threshold (CE, STAT, QON,
PSEL, PG)
1.3 V
V
IH_OTG
Input high threshold (OTG) 1.1 V
V
OUT_LO
Output low saturation voltage Sink current = 5 mA 0.4 V
I
BIAS
High level leakage current (OTG, CE,
STAT , PSEL, PG)
Pull-up rail 1.8 V 1 µA
I
BIAS
High level leakage current (QON) Pull-up rail 3.6 V 8 µA
I
2
C INTERFACE (SDA, SCL, INT)
V
IH
Input high threshold level VPULL-UP = 1.8 V, SDA and SCL 1.3 V
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