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2646 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 10, OCTOBER 2019
VI. CONCLUSION
This paper proposed two load transient enhancement control
techniques: segmented frequency modulator (SFM) and MCW
to reduce the recovery time during heavy-to-light and light-to-
heavy load transients. We verified these two methods through
a proof-of-concept converter prototype implemented in 65-nm
CMOS. The 15-phase interleaved converter implementation
supports output voltages of 1 V from a 2.4-V input supply
attaining 82.8% peak efficiency at an output power density
of 240 mW/mm
2
. From light-to-heavy and heavy-to-light load
transients, the converter can also reach a fast recovery speed
of 5.1 and 4.38 mA/ns, respectively, reflecting a state-of-the-
art transient recovery performance.
R
EFERENCES
[1] M. Steyaert, T. Van Breussegem, H. Meyvaert, P. Callemeyn, and
M. Wens, “DC-DC converters: From discrete towards fully integrated
CMOS,” in Proc. ESSCIRC, Sep. 2011, pp. 42–49.
[2] C. R. Sullivan, D. V. Harburg, J. Qiu, C. G. Levey, and D. Yao,
“Integrating magnetics for on-chip power: A perspective,” IEEE Trans.
Power Electron., vol. 28, no. 9, pp. 4342–4353, Sep. 2013.
[3] S. R. Sanders, E. Alon, H.-P. Le, M. D. Seeman, M. John, and
V. W. Ng, “The road to fully integrated DC–DC conversion via the
switched-capacitor approach,” IEEE Trans. Power Electron., vol. 28,
no. 9, pp. 4146–4155, Sep. 2013.
[4] S. S. Kudva and R. Harjani, “Fully-integrated on-chip DC-DC converter
with a 450X output range,” IEEE J. Solid-State Circuits, vol. 46, no. 8,
pp. 1940–1951, Aug. 2011.
[5] M. D. Seeman and S. R. Sanders, “Analysis and optimization of
switched-capacitor DC–DC converters,” IEEE Tr ans. Power Electron.,
vol. 23, no. 2, pp. 841–851, Mar. 2008.
[6] G. Villar-Piqué, H. J. Bergveld, and E. Alarcón, “Survey and benchmark
of fully integrated switching power converters: Switched-capacitor ver-
sus inductive approach,” IEEE Trans. Power Electron., vol. 28, no. 9,
pp. 4156–4167, Sep. 2013.
[7] R. Jain et al., “A 0.45–1 V fully-integrated distributed switched capacitor
DC-DC converter with high density MIM capacitor in 22 nm tri-gate
CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 917–927,
Apr. 2014.
[8] S. Bang, J.-S. Seo, L. Chang, D. Blaauw, and D. Sylvester, “A low
ripple switched-capacitor voltage regulator using flying capacitance
dithering,” IEEE J. Solid-State Circuits, vol. 51, no. 4, pp. 919–929,
Apr. 2016.
[9] Y. Lu, J. Jiang, and W.-H. Ki, “A multiphase switched-capacitor
DC–DC converter ring with fast transient response and small rip-
ple,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 579–591,
Feb. 2017.
[10] A. Sarafianos and M. Steyaert, “Fully integrated wide input volt-
age range capacitive DC-DC converters: The folding dickson con-
verter,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1560–1570,
Jul. 2015.
[11] T. Tong, S. K. Lee, X. Zhang, D. Brooks, and G. Y. Wei,
“A fully integrated reconfigurable switched-capacitor DC-DC con-
verter with four stacked output channels for voltage stacking appli-
cations,” IEEE J. Solid-State Circuits, vol. 51, no. 9, pp. 2142–2152,
Sep. 2016.
[12] T. M. Van Breussegem and M. S. J. Steyaert, “Monolithic capacitive
DC-DC converter with single Boundary–Multiphase control and voltage
domain stacking in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46,
no. 7, pp. 1715–1727, Jul. 2011.
[13] H.-P. Le, J. Crossley, S. R. Sanders, and E. Alon, “A sub-ns response
fully integrated battery-connected switched-capacitor voltage regulator
delivering 0.19 W/mm
2
at 73% efficiency,” in ISSCC Dig. Tech. Papers,
Feb. 2013, pp. 372–373.
[14] T. M. Andersen et al., “A sub-ns response on-chip switched-capacitor
DC-DC voltage regulator delivering 3.7 W/mm
2
at 90% efficiency using
deep-trench capacitors in 32 nm SOI CMOS,” in ISSCC Dig. Tec h.
Papers, Feb. 2014, pp. 90–91.
[15] T. Souvignet, B. Allard, and S. Trochut, “A fully integrated
switched-capacitor regulator with frequency modulation control in
28-nm FDSOI,” IEEE Trans. Power Electr on., vol. 31, no. 7,
pp. 4984–4994, Jul. 2016.
[16] N. Butzen and M. Steyaert, “A single-topology continuously-scalable-
conversion-ratio fully integrated switched-capacitor DC-DC converter
with 0-to-2.22 V output and 93% peak-efficiency,” in Proc. IEEE Symp.
VLSI Circuits (VLSIC), Jun. 2018, pp. 103–104.
[17] G. V. Piqué, “AA 41-phase switched-capacitor power converter with
3.8 mV output ripple and 81% efficiency in baseline 90 nm CMOS,”
in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,
Feb. 2012, pp. 98–100.
[18] U.-F. Chio et al., “An integrated DC-DC converter with segmented
frequency modulation and multiphase co-work control for fast transient
recovery,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC),
Nov. 2018, pp. 31–32.
[19] H.-P. Le, S. R. Sanders, and E. Alon, “Design techniques for fully
integrated switched-capacitor DC-DC converters,” IEEE J. Solid-State
Circuits, vol. 46, no. 9, pp. 2120–2131, Sep. 2011.
[20] H. Meyvaert, T. Van Breussegem, and M. Steyaert, “A monolithic
0.77 W/mm
2
power dense capacitive DC-DC step-down converter in
90 nm Bulk CMOS,” in Proc. Eur. Solid-State Cir c uits Conf. (ESSCIRC),
Sep. 2011, pp. 483–486.
[21] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed
optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State
Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.
U-Fat Chio (S’07–M’12) received the B.Sc. degree
in electrical engineering and the M.Sc. degree
in communications engineering from National Sun
Yat-sen University, Kaohsiung, Taiwan, in 2002 and
2004, respectively, and the Ph.D. degree from the
University of Macau, Macau, China, in 2012.
From 2004 to 2005, he was with DenMOS Tech-
nology, Inc., Hsinchu, Taiwan. From 2012 to 2017,
he was a Post-Doctoral Fellow with the State Key
Laboratory of Analog and Mixed-Signal VLSI, Uni-
versity of Macau. In 2018, he joined the Chongqing
University of Posts and Telecommunications, Chongqing, China. His research
interests include the designs of power management ICs and high-speed analog-
to-digital converters.
Kuo-Chih Wen was born in Hsinchu, Taiwan.
He received the B.S. degree in electrical engineering
from National Chung Hsing University, Taichung,
Taiwan, in 2006, and the M.S. degree from the
Graduate Institute of Communication Engineering,
Nanyang Technological University (NTU), Singa-
pore, in 2009.
He was a Research Assistant with the State Key
Laboratory of Analog and Mixed-Signal VLSI, Uni-
versity of Macau, Macau, China. He is currently with
Synopsys Macau Ltd., Macau. His research interests
include power management integrated circuit design and high-speed SerDes.