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"K4A8G165WC-DDR4颗粒硬件开发数据手册及规格信息"

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数据手册

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The document "K4A8G165WC_Datasheet_Rev1.5_Apr.17" is a hardware development guide for the K4A8G165WC-DDR4 memory chip manufactured by Samsung Electronics. The datasheet provides detailed information and specifications for the product, enabling developers to leverage the features and capabilities of the memory chip in their hardware designs. It is important to note that Samsung Electronics reserves the right to change products, information, and specifications without notice. This means that the information provided in the datasheet may be subject to change, and developers should always refer to the latest documentation for the most up-to-date information. The products and specifications discussed in the datasheet are for reference purposes only, and the information provided is on an "AS IS" basis, without warranties of any kind. This means that developers should verify the information and specifications provided in the datasheet through their own testing and evaluation to ensure that it meets their specific requirements. Furthermore, it is emphasized that the document and all information discussed therein remain the sole and exclusive property of Samsung Electronics. This means that developers must respect and adhere to any intellectual property rights, including patents, copyrights, mask works, trademarks, or any other rights associated with the product and its documentation. In summary, the "K4A8G165WC_Datasheet_Rev1.5_Apr.17" provides valuable information and specifications for the K4A8G165WC-DDR4 memory chip, allowing hardware developers to understand and integrate this component into their designs. However, it is important to be aware of the potential for changes in products, information, and specifications, as well as to respect the intellectual property rights associated with the product and its documentation. Developers should use the datasheet as a reference and verify the information provided to ensure its suitability for their specific application.

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- 13 -

datasheet DDR4 SDRAM

Rev.1.5

K4A8G165WC

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

NOTE :

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

8.3.2 Differential swing requirement for clock (CK_t - CK_c)

[ Table 8 ] Differential AC & DC Input Levels

NOTE:

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V

IHCA

ILCA

(AC) of ADD/CMD and V

REFCA

;

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

IHCA

(DC) max, V

ILCA

(DC)min) for single-ended signals

as well as the limitations for overshoot and undershoot.

Symbol Parameter

DDR4 -1600/1866/2133 DDR4 -2400/2666

unit NOTE

min max min max

IHdiff

differential input high +0.150 NOTE 3 TBD NOTE 3 V 1

ILdiff

differential input low NOTE 3 -0.150 NOTE 3 TBD V 1

IHdiff

(AC)

differential input high ac

2 x (V

(AC) - V

REF

)

NOTE 3

2 x (V

(AC) - V

REF

)

NOTE 3 V 2

ILdiff

(AC)

differential input low ac NOTE 3

2 x (V

(AC) - V

REF

)

NOTE 3

2 x (V

(AC) - V

REF

)

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

time

tDVAC

.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

- 14 -

datasheet DDR4 SDRAM

Rev.1.5

K4A8G165WC

[ Table 9 ] Allowed time before ringback (tDVAC) for CK_t - CK_c

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK _c have to approximately reach V

SEH

min / V

SEL

max [approximately equal to the ac-levels { V

IH.CA

(AC) / V

IL.CA

(AC)} for ADD/CMD signals]

in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g. if Different value than V

IH.CA

(AC100)/V

IL.CA

(AC100) is used for

ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK _c .

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD signal requirements are with respect to V

REFCA

, the single-ended components of differential signals have a requirement with

respect to V

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended

components of differential signals the requirement to reach V

SEL

max, V

SEH

min has no bearing on timing, but adds a restriction on the common mode

characteristics of these signals.

Slew Rate [V/ns]

tDVAC [ps] @ |V

IH/Ldiff

(AC)| = 200mV

min max

> 4.0 120 -

4.0 115 -

3.0 110 -

2.0 105 -

1.8 100 -

1.6 95 -

1.4 90 -

1.2 85 -

1.0 80 -

< 1.0 80 -

or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

or V

SSQ

SEL

time

- 15 -

datasheet DDR4 SDRAM

Rev.1.5

K4A8G165WC

[ Table 10 ] Single-ended levels for CK_t, CK_c

NOTE :

1. For CK_t - CK_c use V

IH.CA

IL.CA

(AC) of ADD/CMD;

2. V

(AC)/V

(AC) for ADD/CMD is based on V

REFCA

;

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V

IH.CA

(DC) max, V

IL.CA

(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot.

8.3.4 Address, Command and Control Overshoot and Undershoot specifications

[ Table 11 ] AC overshoot/undershoot specification for Address, Command and Control pins

NOTE: 1.The value of VAOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended

DC Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 4

Figure 4. Address, Command and Control Overshoot and Undershoot Definition

Symbol Parameter

DDR4-1600/1866/2133 DDR4 -2400/2666

Unit NOTE

Min Max Min Max

SEH

Single-ended high-level for

CK_t , CK_c

(VDD/2)+0.100 NOTE3 TBD NOTE3 V 1, 2

SEL

Single-ended low-level for

CK_t , CK_c

NOTE3 (VDD/2)-0.100 NOTE3 TBD V 1, 2

Parameter Symbol

Specification

Unit NOTE

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Maximum peak amplitude above VAOS VAOSP 0.06 TBD V

Upper boundary of overshoot area AAOS1 VAOS VDD +0.24 TBD V 1

Maximum peak amplitude allowed for undershoot

VAUS 0.30 TBD V

Maximum overshoot area per 1 tCK above VAOS AAOS2 0.0083 0.0071 0.0062 0.0055 TBD V-ns

Maximum overshoot area per 1 tCK between VDD and VAOS AAOS1 0.2550 0.2185 0.1914 0.1699 TBD V-ns

Maximum undershoot area per 1 tCK below VSS AAUS 0.2644 0.2265 0.1984 0.1762 TBD V-ns

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

AOS1

AUS

Volts

(V)

1 tCK

AOSP

AOS2

AOS

AUS

- 16 -

datasheet DDR4 SDRAM

Rev.1.5

K4A8G165WC

8.3.5 Clock Overshoot and Undershoot Specifications

[ Table 12 ] AC overshoot/undershoot specification for Clock

NOTE: The value of VCOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 4

Figure 5. Clock Overshoot and Undershoot Definition

Parameter Symbol

Specification

Unit NOTE

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Maximum peak amplitude above VCOS VCOSP 0.06 TBD V

Upper boundary of overshoot area ADOS1 VCOS VDD +0.24 TBD V 1

Maximum peak amplitude allowed for undershoot VCUS 0.30 TBD V

Maximum overshoot area per 1 UI above VCOS

ACOS2 0.0038 0.0032 0.0028 0.0025 TBD V-ns

Maximum overshoot area per 1 UI between VDD and VDOS ACOS1 0.1125 0.0964 0.0844 0.0750 TBD V-ns