PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
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8.4.2 Electrical Idle........................................................................................................ 1026
8.4.3 EIEOS for M-PCIe ................................................................................................ 1026
8.4.4 Lane Polarity Inversion ........................................................................................ 1026
8.4.5 Fast Training Sequence (FTS) .............................................................................. 1026
8.4.6 LINK Data RATE .................................................................................................. 1027
8.4.7 LINK Width ........................................................................................................... 1027
8.4.8 LANE-to-LANE De-skew ...................................................................................... 1027
8.4.9 LINK Training and Status State Machine (LTSSM) ............................................. 1027
8.4.10 Entry to HIBERN8 ............................................................................................ 1049
8.5 RECEIVER ERROR ....................................................................................................... 1049
8.6 CLOCK TOLERANCE COMPENSATION ......................................................................... 1050
8.7 DYNAMIC LINK BANDWIDTH MANAGEMENT ........................................................... 1050
8.7.1 LINK Rate Series and Speed Management ........................................................... 1050
8.7.2 LINK Width Management ..................................................................................... 1051
8.7.3 Dynamic LINK Re-Configuration ......................................................................... 1051
8.8 M-PHY REGISTERS ................................................................................................... 1054
8.8.1 M-PHY Capability Registers................................................................................. 1054
8.8.2 M-PHY Configuration Attributes .......................................................................... 1061
9 ELECTRICAL SUB-BLOCK ....................................................................................... 1063
9.1 ELECTRICAL SPECIFICATION ORGANIZATION ............................................................ 1063
9.2 INTEROPERABILITY CRITERIA .................................................................................... 1063
9.2.1 Data Rates ............................................................................................................. 1063
9.2.2 Refclk Architectures .............................................................................................. 1063
9.3 TRANSMITTER SPECIFICATION ................................................................................... 1063
9.3.1 Measurement Setup for Characterizing Transmitters........................................... 1063
9.3.2 Voltage Level Definitions ...................................................................................... 1065
9.3.3 Tx Voltage Parameters ......................................................................................... 1066
9.3.4 Transmitter Margining.......................................................................................... 1075
9.3.5 Tx Jitter Parameters ............................................................................................. 1076
9.3.6 Tx and Rx Return Loss .......................................................................................... 1086
9.3.7 Transmitter PLL Bandwidth and Peaking ............................................................ 1088
9.3.8 Data Rate Independent Tx Parameters ................................................................. 1088
9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1090
9.4.1 Receiver Stressed Eye Specification ..................................................................... 1090
9.4.2 Stressed Eye Test................................................................................................... 1095
9.4.3 Common Receiver Parameters ............................................................................. 1102
9.4.4 Low Frequency and Miscellaneous Signaling Requirements ............................... 1105
9.5 CHANNEL TOLERANCING ........................................................................................... 1107
9.5.1 Channel Compliance Testing ................................................................................ 1107
9.6 REFCLK SPECIFICATIONS ........................................................................................... 1116
9.6.1 Refclk Test Setup ................................................................................................... 1116
9.6.2 Data Rate Independent Refclk Parameters ........................................................... 1117
9.6.3 Refclk Architectures Supported............................................................................. 1118
9.6.4 Filtering Functions Applied to Raw Data ............................................................. 1118
9.6.5 Common Refclk Rx Architecture (CC) .................................................................. 1120
9.6.6 Jitter Limits for Refclk Architectures .................................................................... 1123