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首页1-DDI0487A_a_2_armv8_arm_arch_reference_manual.pdf
1-DDI0487A_a_2_armv8_arm_arch_reference_manual.pdf
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ARMv8体系结构原文,描述了ARM64的寄存器,指令的CPU相关体系结构,可以用于飞腾和鲲鹏CPU的学习
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Preface
Using this manual
xvi Copyright © 2013 ARM. All rights reserved. ARM DDI 0487A.a-2
Confidential - Draft - Beta ID061413
Using this manual
The information in this manual is organized into parts, as described in this section.
Part A, Introduction and Architecture Overview
Part A gives an overview of the ARMv8-A architecture profile, including its place in the range of ARM processor
architectures. It introduces the terminology used to describe the architecture, that ARMv8 changes significantly. It
gives an overview of the Executions states, AArch64 and AArch32. It contains the following chapter:
Chapter A1 Introduction to the ARMv8 Architecture
Read this for an introduction to the ARMv8 architecture.
Part B, The AArch64 Application Level Architecture
Part B describes the application level view of the architecture in AArch64 state. It contains the following chapters:
Chapter B1 The AArch64 Application Level Programmers’ Model
Read this for an application level description of the programmers’ model for software executing in
AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.
Chapter B2 The AArch64 Application Level Memory Model
Read this for an application level description of the memory model for software executing in
AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64
state. It includes information about ARM memory types, attributes, and memory access controls.
Part C, The A64 Instruction Set
Part C describes the A64 instruction set, which can only be used in AArch64 state. It contains the following
chapters:
Chapter C1 The A64 Instruction Set
Read this for a description of the A64 Instruction Set and details of instruction operation that are
common to several instructions.
Chapter C2 A64 Instruction Set Overview
Read this for an overview of the individual A64 instructions, that are divided into five functional
groups.
Chapter C3 A64 Instruction Set Encoding
Read this for a description of the A64 Instruction Set encoding.
Chapter C4 The AArch64 System Instruction Class
Read this for a description of the AArch64 system instructions and register descriptions, and the
system instruction class encoding space.
Chapter C5 A64 Base Instruction Descriptions
Read this for information on key aspects of the A64 base instructions and for descriptions of the
individual instructions, which are listed in alphabetical order.
Chapter C6 A64 SIMD and Floating-point Instruction Descriptions
Read this for information on key aspects of the A64 Advanced SIMD and floating-point instructions
and for descriptions of the individual instructions, which are listed in alphabetical order.
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Preface
Using this manual
ARM DDI 0487A.a-2 Copyright © 2013 ARM. All rights reserved. xvii
ID061413 Confidential - Draft - Beta
Part D, The AArch64 System Level Architecture
Part D describes the AArch64 the system level view of the architecture. It contains the following chapters:
Chapter D1 The AArch64 System Level Programmers’ Model
Read this for a description of the AArch64 system level view of the programmers’ model.
Chapter D2 Software Debug Events
Read this for an introduction to, and a description of, different software debug events.
Chapter D3 The Debug Exception Model
Read this for a description of debug exceptions.
Chapter D4 The AArch64 System Level Memory Model
Read this for a description of the AArch64 system level view of the general features of the memory
system.
Chapter D5 The AArch64 Virtual Memory System Architecture
Read this for a system level view of the AArch64 Virtual Memory System Architecture (VMSA),
the memory system architecture of an ARMv8 implementation that is executing in AArch64 state.
Chapter D6 The Performance Monitors Extension
Read this for a description of an implementation of the ARM Performance Monitors, that are an
optional non-invasive debug component.
Chapter D7 The Generic Timer
Read this for a description of an implementation of the ARM Generic Timer, that is an extension to
an ARMv8 processor implementation.
Chapter D8 AArch64 System Register Descriptions
Read this for an introduction to, and description of, each of the AArch64 system registers.
Part E, The AArch32 Application Level Architecture
Part E describes the AArch32 application level view of the architecture. It contains the following chapters:
Chapter E1 The AArch32 Application Level Programmers’ Model
Read this for an application level description of the programmers’ model for software executing in
AArch32 state. It describes execution at EL0 when EL0 is using AArch32 state.
Chapter E2 The AArch32 Application Level Memory Model
Read this for an application level description of the memory model for software executing in
AArch32 state. It describes the memory model for execution in EL0 when EL0 is using AArch32
state. It includes information about ARM memory types, attributes, and memory access controls.
Part F, The AArch32 Instruction Sets
Part F describes the T32 and A32 instruction sets, that are used in AArch32 state. It contains the following chapters:
Chapter F1 The AArch32 Instruction Sets Overview
Read this for an overview of the T32 and A32 instruction sets.
Chapter F2 About the T32 and A32 Instruction Descriptions
Read this for a description of the T32 and A32 instructions.
Chapter F3 T32 Base Instruction Set Encoding
Read this for an introduction to the T32 instruction set and a description of how the T32 instruction
set uses the ARM programmers’ model.
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Preface
Using this manual
xviii Copyright © 2013 ARM. All rights reserved. ARM DDI 0487A.a-2
Confidential - Draft - Beta ID061413
Chapter F4 A32 Base Instruction Set Encoding
Read this for a description of the A32 base instruction set encoding.
Chapter F5 T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings
Read this for an overview of the T32 and A32 Advanced SIMD and floating-point instruction sets.
Chapter F6 ARMv8 Changes to the T32 and A32 Instruction Sets
Read this for a summary of the changes that are introduced to the T32 and A32 instruction sets in
ARMv8.
Chapter F7 T32 and A32 Base Instruction Set Instruction Descriptions
Read this for a description of each T32 and A32 base instruction.
Chapter F8 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions
Read this for a description of each T32 and A32 Advanced SIMD and floating-point instruction.
Part G, The AArch32 System Level Architecture
Part G describes the AArch32 system level view of the architecture. It contains the following chapters:
Chapter G1 The AArch32 System Level Programmers’ Model
Read this for a description of the AArch32 system level view of the programmers’ model for
execution in an Exception level that is using AArch32.
Chapter G2 The AArch32 System Level Memory Model
Read this for a system level view of the general features of the memory system.
Chapter G3 The AArch32 Virtual Memory System Architecture
Read this for a description of the AArch32 Virtual Memory System Architecture (VMSA).
Chapter G4 AArch32 System Register Descriptions
Read this for a description of each of the AArch32 system registers.
Part H, The ARMv8 Debug Architecture, for External Debug
Part H describes the architecture for external debug. It contains the following chapters:
Chapter H1 Introduction to the ARMv8 Debug Architecture
Read this for an introduction to self-hosted and external debug, and a definition of the scope of this
part of the manual.
Chapter H2 Debug State
Read this for a description of debug state, which the processor might enter as the result of a Halting
debug event.
Chapter H3 Halting Debug Events
Read this for a description of the external debug events referred to as Halting debug events.
Chapter H4 The Debug Communication Channel and Instruction Transfer Register
Read this for a description of the communication between a debugger and the processor debug logic
using the Debug Communications Channel and the Instruction Transfer register.
Chapter H5 The Embedded Cross Trigger Interface
Read this for a description of the embedded cross-trigger interface.
Chapter H6 Debug Reset and Powerdown Support
Read this for a description of reset and powerdown support in the Debug architecture.
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Preface
Using this manual
ARM DDI 0487A.a-2 Copyright © 2013 ARM. All rights reserved. xix
ID061413 Confidential - Draft - Beta
Chapter H7 The Sample-based Profiling Extension
Read this for a description of the Sample-based Profiling extension that is an optional extension to
the ARMv8 architecture.
Chapter H8 About the External Debug Registers
Read this for some additional information about the external debug registers.
Chapter H9 External Debug Register Descriptions
Read this for a description of each external debug register.
Part I, Memory-mapped Components of the ARMv8 Architecture
Part I describes the memory-mapped components in the architecture. It contains the following chapters:
Chapter I1 Memory-Mapped System Register Descriptions
Read this for a description of each memory-mapped system register.
Chapter I2 System Level Implementation of the Generic Timer
Read this for a definition of a system level implementation of the Generic Timer.
Chapter I3 Recommended Memory-mapped Interfaces to the Performance Monitors
Read this for a description of the recommended memory-mapped and external debug interfaces to
the Performance Monitors.
Part J, Appendixes
This manual contains the following appendixes:
Appendix A Recommended External Debug Interface
Read this for a description of the recommended external debug interface.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix B Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION
DEFINED Events
Read this for a description of ARM recommendations for the use of the
IMPLEMENTATION DEFINED
event numbers.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix C Example OS Save and Restore sequences
Read this for software examples that perform the OS Save and Restore sequences for an ARMv8
debug implementation.
Note
Chapter H6 Debug Reset and Powerdown Support describes the OS Save and Restore mechanism.
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Preface
Using this manual
xx Copyright © 2013 ARM. All rights reserved. ARM DDI 0487A.a-2
Confidential - Draft - Beta ID061413
Appendix D Additional Guidance
Read this for information about implementing and using the ARM architecture.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix E Barrier Litmus Tests
Read this for examples of the use of barrier instructions provided by the ARMv8 architecture.
Note
This description is not part of the ARM architecture specification. It is included here as
supplementary information, for the convenience of developers and users who might require this
information.
Appendix F Shared Pseudocode Definition
Read this for the pseudocode definitions that are shared between AArch32 and AArch64.
Appendix G AArch32 Pseudocode Definition
Read this for definitions of the AArch32 pseudocode.
Appendix H Pseudocode Index
Read this for an index of the pseudocode.
Appendix I Registers Index
Read this for an alphabetic and functional index of AArch32 and AArch64 registers, and
memory-mapped registers.
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