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ARM DDI 0487A.a-2 (ID061413)

ARM

Architecture Reference Manual

ARMv8, for ARMv8-A architecture profile

Printed on: June 14, 2013

Confidential - Draft - Beta

Confidential - Draft - Beta ID061413

ARM Architecture Reference Manual

ARMv8, for ARMv8-A architecture profile

Release Information

The following releases of this document have been made.

Proprietary Notice

This ARM Architecture Reference Manual is CONFIDENTIAL and any use by you is subject to the terms of the agreement

between you and ARM or the terms of the agreement between you and the party authorised by ARM to disclose this document to

you.

This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information

contained herein may be protected by one or more patents or pending patent applications. No part of this ARM Architecture

Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license,

express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture

Reference Manual.

Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not

use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture

infringe any third party patents.

This ARM Architecture Reference Manual is provided “as is”. ARM provides no warranties express implied or statutory,

including but not limited to, warranties of merchantability, satisfactory quality, fitness for a particular purpose, or

non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or that any

practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third party patents,

copyrights, trade secrets, or other rights. ARM makes no representation with respect to, and has undertaken no analysis to identify

or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This ARM Architecture Reference Manual may include technical inaccuracies or typographical errors.

To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss,

lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless

of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this ARM Architecture

Reference Manual, even if ARM has been advised of the possibility of such damages.

This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure

of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof

is not exported, directly or indirectly, in violation of such export laws. ARM may make changes to this document at any time and

without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this

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Words and logos marked with ® or TM are registered trademarks or trademarks of ARM Limited in the EU or elsewhere. Other

brands and names mentioned herein may be the trademarks of their respective owners.

ARM Limited, Company 02557590 registered in England.

10 Fulbourn Road Cambridge, England CB1 9NJ.

In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as appropriate”.

Release history

Date Issue Confidentiality Change

30 April 2013 A.a-1 Confidential-Beta Draft Beta draft of first issue, limited circulation

12 June 2013 A.a-2 Confidential-Beta Draft Second beta draft of first issue

ID061413 Confidential - Draft - Beta

Contents

ARM Architecture Reference Manual ARMv8, for

ARMv8-A architecture profile

Preface

About this manual ..................................................................................................... xiv

Using this manual ...................................................................................................... xvi

Conventions .............................................................................................................. xxi

Additional reading ................................................................................................... xxiii

Feedback ................................................................................................................ xxiv

Part A ARMv8 Architecture Introduction and Overview

Chapter A1 Introduction to the ARMv8 Architecture

A1.1 About the ARM architecture ................................................................................ A1-28

A1.2 Architecture profiles ............................................................................................ A1-30

A1.3 ARMv8 architectural concepts ............................................................................. A1-31

A1.4 Supported data types .......................................................................................... A1-34

A1.5 Floating-point and Advanced SIMD support ........................................................ A1-44

A1.6 Cryptographic Extension ..................................................................................... A1-50

A1.7 The ARM memory model .................................................................................... A1-51

Part B The AArch64 Application Level Architecture

Chapter B1 The AArch64 Application Level Programmers’ Model

B1.1 About the Application level programmers’ model ................................................ B1-56

B1.2 Registers in AArch64 Execution state ................................................................. B1-57

B1.3 Software control features and EL0 ...................................................................... B1-63

Confidential - Draft - Beta ID061413

Chapter B2 The AArch64 Application Level Memory Model

B2.1 Address space .................................................................................................... B2-66

B2.2 Memory type overview ........................................................................................ B2-67

B2.3 Caches and memory hierarchy ........................................................................... B2-68

B2.4 Alignment support ............................................................................................... B2-73

B2.5 Endian support .................................................................................................... B2-75

B2.6 Atomicity in the ARM architecture ....................................................................... B2-78

B2.7 Memory ordering ................................................................................................. B2-81

B2.8 Memory types and attributes ............................................................................... B2-88

B2.9 Mismatched memory attributes ........................................................................... B2-97

B2.10 Synchronization and semaphores ....................................................................... B2-99

Part C The AArch64 Instruction Set

Chapter C1 The A64 Instruction Set

C1.1 Introduction ....................................................................................................... C1-110

C1.2 Structure of the A64 assembler language ......................................................... C1-111

C1.3 Address generation ........................................................................................... C1-117

C1.4 Instruction aliases ............................................................................................. C1-120

Chapter C2 A64 Instruction Set Overview

C2.1 Branches, Exception Generating, and System Instructions .............................. C2-122

C2.2 Loads and Stores .............................................................................................. C2-126

C2.3 Data processing (immediate) ............................................................................ C2-138

C2.4 Data processing (register) ................................................................................. C2-143

C2.5 Data processing - SIMD and floating-point ........................................................ C2-150

Chapter C3 A64 Instruction Set Encoding

C3.1 A64 instruction index by encoding .................................................................... C3-174

C3.2 Branches, exception generating and system instructions ................................. C3-175

C3.3 Loads and stores ............................................................................................... C3-178

C3.4 Data processing - immediate ............................................................................. C3-195

C3.5 Data processing - register ................................................................................. C3-198

C3.6 Data processing - SIMD and floating point ........................................................ C3-205

Chapter C4 The AArch64 System Instruction Class

C4.1 About the System instruction and System register descriptions ....................... C4-232

C4.2 The System instruction class encoding space .................................................. C4-234

C4.3 PSTATE and special purpose registers ............................................................ C4-251

C4.4 A64 system instructions for cache maintenance ............................................... C4-306

C4.5 A64 system instructions for address translation ................................................ C4-321

C4.6 A64 system instructions for TLB maintenance .................................................. C4-333

Chapter C5 A64 Base Instruction Descriptions

C5.1 Introduction ....................................................................................................... C5-370

C5.2 Register size ..................................................................................................... C5-371

C5.3 Use of the PC .................................................................................................... C5-372

C5.4 Use of the Stack pointer .................................................................................... C5-373

C5.5 Condition flags and related instructions ............................................................ C5-374

C5.6 Supported addressing modes ........................................................................... C5-375

C5.7 Alphabetical list of instructions .......................................................................... C5-376

Chapter C6 A64 SIMD and Floating-point Instruction Descriptions

C6.1 Introduction ....................................................................................................... C6-766

C6.2 Supported addressing modes ........................................................................... C6-767

C6.3 Register size ..................................................................................................... C6-768

C6.4 Scalar floating-point .......................................................................................... C6-769

ID061413 Confidential - Draft - Beta

C6.5 Advanced SIMD Instructions ............................................................................. C6-770

C6.6 Alphabetical list of floating-point and Advanced SIMD instructions ................... C6-771

Part D The AArch64 System Level Architecture

Chapter D1 The AArch64 System Level Programmers’ Model

D1.1 Exception level ................................................................................................ D1-1434

D1.2 Exception terminology ..................................................................................... D1-1435

D1.3 Execution state ................................................................................................ D1-1437

D1.4 Security state .................................................................................................. D1-1438

D1.5 Virtualization .................................................................................................... D1-1440

D1.6 Registers for instruction processing and exception handling .......................... D1-1442

D1.7 Process state, PSTATE .................................................................................. D1-1447

D1.8 Program counter and stack pointer alignment ................................................. D1-1449

D1.9 Reset ............................................................................................................... D1-1451

D1.10 Exception entry ............................................................................................... D1-1454

D1.11 Exception return .............................................................................................. D1-1462

D1.12 The Exception level hierarchy ......................................................................... D1-1466

D1.13 Synchronous exception types, routing and priorities ....................................... D1-1472

D1.14 Asynchronous exception types, routing, masking and priorities ...................... D1-1478

D1.15 Trapping functionality to higher Exception levels ............................................ D1-1484

D1.16 System calls .................................................................................................... D1-1509

D1.17 Use of the ESR_EL1, ESR_EL2, and ESR_EL3 ............................................ D1-1510

D1.18 Mechanisms for entering a low-power state .................................................... D1-1530

D1.19 Self-hosted debug ........................................................................................... D1-1536

D1.20 Performance Monitors extension ..................................................................... D1-1538

D1.21 Interprocessing ................................................................................................ D1-1539

D1.22 Supported configurations ................................................................................ D1-1549

Chapter D2 Software Debug Events

D2.1 Introduction to software debug events ............................................................ D2-1554

D2.2 Legacy debug events ...................................................................................... D2-1558

D2.3 Understanding the descriptions for AArch64 state and AArch32 state ........... D2-1559

D2.4 Software Breakpoint Instruction debug events ................................................ D2-1560

D2.5 Breakpoint debug events ................................................................................ D2-1564

D2.6 Watchpoint debug events ................................................................................ D2-1602

D2.7 Vector Catch debug events ............................................................................. D2-1621

D2.8 Software Step debug events ........................................................................... D2-1630

D2.9 Synchronization and software debug events .................................................. D2-1652

Chapter D3 The Debug Exception Model

D3.1 Introduction to debug exceptions .................................................................... D3-1654

D3.2 The debug exceptions enable controls ........................................................... D3-1655

D3.3 Routing debug exceptions ............................................................................... D3-1656

D3.4 Enabling debug exceptions from the current Exception level and Security state D3-1661

D3.5 The effect of powerdown on debug exceptions ............................................... D3-1665

D3.6 Summary of permitted routing and enabling of debug exceptions .................. D3-1666

D3.7 Debug exception behavior .............................................................................. D3-1669

D3.8 Pseudocode descriptions of debug exceptions ............................................... D3-1674

Chapter D4 The AArch64 System Level Memory Model

D4.1 About the memory system architecture ........................................................... D4-1678

D4.2 Address space ................................................................................................ D4-1679

D4.3 Mixed-endian support ...................................................................................... D4-1680

D4.4 Cache support ................................................................................................. D4-1681

D4.5 Memory barrier instructions ............................................................................. D4-1700

D4.6 Pseudocode details of general memory system instructions .......................... D4-1701

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