NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf

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PCI Express® Base Specification Revision 5.0

Version 1.0

22 May 2019

PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are

trademarks, registered trademarks, or servicemarks of their respective owners.

Contact PCI-SIG Membership Services for questions about membership in the PCI-SIG or to obtain the latest revision of

this specification. Contact PCI-SIG Technical Support for technical questions about this specification.

DISCLAIMER

PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and

assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to

update the information contained herein.

This PCI Specification is provided “as is” without any warranties of any kind, including any warranty of merchantability,

non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal,

specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of

information in this specification. This document itself may not be modified in any way, including by removing the

property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.

All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

5.0-1.0-PUB — PCI Express® Base Specification Revision 5.0 Version 1.0

Table of Contents

1. Introduction.......................................................................................................................................................................89

1.1 A Third Generation I/O Interconnect.................................................................................................................................89

1.2 PCI Express Link.................................................................................................................................................................90

1.3 PCI Express Fabric Topology .............................................................................................................................................92

1.3.1 Root Complex ............................................................................................................................................................92

1.3.2 Endpoints...................................................................................................................................................................93

1.3.2.1 Legacy Endpoint Rules ......................................................................................................................................93

1.3.2.2 PCI Express Endpoint Rules...............................................................................................................................94

1.3.2.3 Root Complex Integrated Endpoint Rules........................................................................................................94

1.3.3 Switch.........................................................................................................................................................................95

1.3.4 Root Complex Event Collector ..................................................................................................................................96

1.3.5 PCI Express to PCI/PCI-X Bridge................................................................................................................................96

1.4 Hardware/Soware Model for Discovery, Configuration and Operation........................................................................96

1.5 PCI Express Layering Overview.........................................................................................................................................97

1.5.1 Transaction Layer ......................................................................................................................................................99

1.5.2 Data Link Layer ..........................................................................................................................................................99

1.5.3 Physical Layer............................................................................................................................................................99

1.5.4 Layer Functions and Services .................................................................................................................................100

1.5.4.1 Transaction Layer Services .............................................................................................................................100

1.5.4.2 Data Link Layer Services..................................................................................................................................101

1.5.4.3 Physical Layer Services ...................................................................................................................................101

1.5.4.4 Inter-Layer Interfaces ......................................................................................................................................102

1.5.4.4.1 Transaction/Data Link Interface..............................................................................................................102

1.5.4.4.2 Data Link/Physical Interface ...................................................................................................................102

2. Transaction Layer Specification......................................................................................................................................103

2.1 Transaction Layer Overview............................................................................................................................................103

2.1.1 Address Spaces, Transaction Types, and Usage.....................................................................................................104

2.1.1.1 Memory Transactions......................................................................................................................................104

2.1.1.2 I/O Transactions...............................................................................................................................................104

2.1.1.3 Configuration Transactions.............................................................................................................................105

2.1.1.4 Message Transactions .....................................................................................................................................105

2.1.2 Packet Format Overview .........................................................................................................................................105

2.2 Transaction Layer Protocol - Packet Definition..............................................................................................................107

2.2.1 Common Packet Header Fields...............................................................................................................................107

2.2.2 TLPs with Data Payloads - Rules .............................................................................................................................110

2.2.3 TLP Digest Rules ......................................................................................................................................................113

2.2.4 Routing and Addressing Rules................................................................................................................................113

2.2.4.1 Address-Based Routing Rules.........................................................................................................................113

2.2.4.2 ID Based Routing Rules ...................................................................................................................................115

2.2.5 First/Last DW Byte Enables Rules............................................................................................................................117

2.2.6 Transaction Descriptor............................................................................................................................................119

2.2.6.1 Overview ..........................................................................................................................................................119

2.2.6.2 Transaction Descriptor - Transaction ID Field................................................................................................120

2.2.6.3 Transaction Descriptor - Attributes Field........................................................................................................125

2.2.6.4 Relaxed Ordering and ID-Based Ordering Attributes.....................................................................................126

2.2.6.5 No Snoop Attribute..........................................................................................................................................126

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2.2.6.6 Transaction Descriptor - Traic Class Field ....................................................................................................127

2.2.7 Memory, I/O, and Configuration Request Rules.....................................................................................................127

2.2.7.1 TPH Rules.........................................................................................................................................................131

2.2.8 Message Request Rules ...........................................................................................................................................133

2.2.8.1 INTx Interrupt Signaling - Rules ......................................................................................................................135

2.2.8.2 Power Management Messages........................................................................................................................139

2.2.8.3 Error Signaling Messages ................................................................................................................................140

2.2.8.4 Locked Transactions Support .........................................................................................................................141

2.2.8.5 Slot Power Limit Support................................................................................................................................142

2.2.8.6 Vendor_Defined Messages..............................................................................................................................143

2.2.8.6.1 PCI-SIG-Defined VDMs.............................................................................................................................144

2.2.8.6.2 LN Messages.............................................................................................................................................145

2.2.8.6.3 Device Readiness Status (DRS) Message.................................................................................................146

2.2.8.6.4 Function Readiness Status Message (FRS Message) ..............................................................................147

2.2.8.6.5 Hierarchy ID Message ..............................................................................................................................148

2.2.8.7 Ignored Messages............................................................................................................................................150

2.2.8.8 Latency Tolerance Reporting (LTR) Message..................................................................................................150

2.2.8.9 Optimized Buer Flush/Fill (OBFF) Message..................................................................................................151

2.2.8.10 Precision Time Measurement (PTM) Messages..............................................................................................152

2.2.9 Completion Rules ....................................................................................................................................................153

2.2.10 TLP Prefix Rules .......................................................................................................................................................156

2.2.10.1 Local TLP Prefix Processing.............................................................................................................................157

2.2.10.1.1 Vendor Defined Local TLP Prefix.............................................................................................................157

2.2.10.2 End-End TLP Prefix Processing .......................................................................................................................157

2.2.10.2.1 Vendor Defined End-End TLP Prefix .......................................................................................................159

2.2.10.2.2 Root Ports with End-End TLP Prefix Supported.....................................................................................159

2.3 Handling of Received TLPs..............................................................................................................................................160

2.3.1 Request Handling Rules ..........................................................................................................................................163

2.3.1.1 Data Return for Read Requests .......................................................................................................................169

2.3.2 Completion Handling Rules....................................................................................................................................175

2.4 Transaction Ordering.......................................................................................................................................................177

2.4.1 Transaction Ordering Rules.....................................................................................................................................177

2.4.2 Update Ordering and Granularity Observed by a Read Transaction.....................................................................181

2.4.3 Update Ordering and Granularity Provided by a Write Transaction .....................................................................182

2.5 Virtual Channel (VC) Mechanism.....................................................................................................................................182

2.5.1 Virtual Channel Identification (VC ID).....................................................................................................................184

2.5.2 TC to VC Mapping.....................................................................................................................................................185

2.5.3 VC and TC Rules .......................................................................................................................................................186

2.6 Ordering and Receive Buer Flow Control.....................................................................................................................187

2.6.1 Flow Control Rules...................................................................................................................................................188

2.6.1.1 FC Information Tracked by Transmitter..........................................................................................................192

2.6.1.2 FC Information Tracked by Receiver...............................................................................................................194

2.7 Data Integrity ...................................................................................................................................................................198

2.7.1 ECRC Rules...............................................................................................................................................................198

2.7.2 Error Forwarding .....................................................................................................................................................202

2.7.2.1 Error Forwarding Usage Model .......................................................................................................................202

2.7.2.2 Rules For Use of Data Poisoning .....................................................................................................................203

2.8 Completion Timeout Mechanism ...................................................................................................................................204

2.9 Link Status Dependencies...............................................................................................................................................205

2.9.1 Transaction Layer Behavior in DL_Down Status ....................................................................................................205

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2.9.2 Transaction Layer Behavior in DL_Up Status .........................................................................................................206

2.9.3 Transaction Layer Behavior During Downstream Port Containment....................................................................206

3. Data Link Layer Specification..........................................................................................................................................209

3.1 Data Link Layer Overview................................................................................................................................................209

3.2 Data Link Control and Management State Machine.......................................................................................................210

3.2.1 Data Link Control and Management State Machine Rules.....................................................................................211

3.3 Data Link Feature Exchange............................................................................................................................................214

3.4 Flow Control Initialization Protocol................................................................................................................................215

3.4.1 Flow Control Initialization State Machine Rules.....................................................................................................215

3.4.2 Scaled Flow Control.................................................................................................................................................220

3.5 Data Link Layer Packets (DLLPs) .....................................................................................................................................221

3.5.1 Data Link Layer Packet Rules ..................................................................................................................................221

3.6 Data Integrity Mechansisms............................................................................................................................................227

3.6.1 Introduction.............................................................................................................................................................227

3.6.2 LCRC, Sequence Number, and Retry Management (TLP Transmitter)..................................................................228

3.6.2.1 LCRC and Sequence Number Rules (TLP Transmitter) ..................................................................................228

3.6.2.2 Handling of Received DLLPs............................................................................................................................235

3.6.3 LCRC and Sequence Number (TLP Receiver)..........................................................................................................238

3.6.3.1 LCRC and Sequence Number Rules (TLP Receiver)........................................................................................239

4. Physical Layer Logical Block ...........................................................................................................................................245

4.1 Introduction.....................................................................................................................................................................245

4.2 Logical Sub-block ............................................................................................................................................................245

4.2.1 Encoding for 2.5 GT/s and 5.0 GT/s Data Rates .......................................................................................................246

4.2.1.1 Symbol Encoding.............................................................................................................................................246

4.2.1.1.1 Serialization and De-serialization of Data..............................................................................................246

4.2.1.1.2 Special Symbols for Framing and Link Management (K Codes)............................................................247

4.2.1.1.3 8b/10b Decode Rules...............................................................................................................................248

4.2.1.2 Framing and Application of Symbols to Lanes...............................................................................................249

4.2.1.3 Data Scrambling ..............................................................................................................................................252

4.2.2 Encoding for 8.0 GT/s and Higher Data Rates.........................................................................................................253

4.2.2.1 Lane Level Encoding........................................................................................................................................254

4.2.2.2 Ordered Set Blocks..........................................................................................................................................256

4.2.2.2.1 Block Alignment ......................................................................................................................................256

4.2.2.3 Data Blocks ......................................................................................................................................................257

4.2.2.3.1 Framing Tokens .......................................................................................................................................258

4.2.2.3.2 Transmitter Framing Requirements........................................................................................................263

4.2.2.3.3 Receiver Framing Requirements.............................................................................................................264

4.2.2.3.4 Recovery from Framing Errors ................................................................................................................266

4.2.2.4 Scrambling.......................................................................................................................................................267

4.2.2.5 Precoding.........................................................................................................................................................272

4.2.2.6 Loopback with 128b/130b Code.....................................................................................................................274

4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates..........................................................................274

4.2.3.1 Rules for Transmitter Coeicients ..................................................................................................................286

4.2.3.2 Encoding of Presets.........................................................................................................................................287

4.2.4 Link Initialization and Training ...............................................................................................................................288

4.2.4.1 Training Sequences .........................................................................................................................................288

4.2.4.2 Alternate Protocol Negotiation.......................................................................................................................298

4.2.4.3 Electrical Idle Sequences (EIOS) .....................................................................................................................301

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