Apollo2Blue:超低功耗微控制器，长续航电池电子设备新标杆

apollo2

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Apollo2 Blue Datasheet

DS-A2B-0p2 Page 16 of 536 2017 Ambiq Micro, Inc.

Table 137: BUCK Register ....................................................................................................... 103

Table 138: BUCK Register Bits ............................................................................................... 103

Table 139: BUCK2 Register ..................................................................................................... 104

Table 140: BUCK2 Register Bits ............................................................................................. 104

Table 141: BUCK3 Register ..................................................................................................... 105

Table 142: BUCK3 Register Bits ............................................................................................. 105

Table 143: LDOREG2 Register ................................................................................................ 106

Table 144: LDOREG2 Register Bits ........................................................................................ 106

Table 145: BODPORCTRL Register ....................................................................................... 108

Table 146: BODPORCTRL Register Bits ................................................................................ 108

Table 147: ADCCAL Register ................................................................................................. 108

Table 148: ADCCAL Register Bits .......................................................................................... 109

Table 149: ADCBATTLOAD Register .................................................................................... 109

Table 150: ADCBATTLOAD Register Bits ............................................................................ 109

Table 151: ADCREFCOMP Register ....................................................................................... 110

Table 152: ADCREFCOMP Register Bits ............................................................................... 110

Table 153: XTALGENCTRL Register ..................................................................................... 110

Table 154: XTALGENCTRL Register Bits ............................................................................. 111

Table 155: BOOTLOADERLOW Register .............................................................................. 111

Table 156: BOOTLOADERLOW Register Bits ...................................................................... 111

Table 157: SHADOWVALID Register .................................................................................... 112

Table 158: SHADOWVALID Register Bits ............................................................................ 112

Table 159: ICODEFAULTADDR Register ............................................................................. 112

Table 160: ICODEFAULTADDR Register Bits ...................................................................... 113

Table 161: DCODEFAULTADDR Register ............................................................................ 113

Table 162: DCODEFAULTADDR Register Bits .................................................................... 113

Table 163: SYSFAULTADDR Register .................................................................................. 113

Table 164: SYSFAULTADDR Register Bits ........................................................................... 114

Table 165: FAULTSTATUS Register ...................................................................................... 114

Table 166: FAULTSTATUS Register Bits .............................................................................. 114

Table 167: FAULTCAPTUREEN Register ............................................................................. 115

Table 168: FAULTCAPTUREEN Register Bits ...................................................................... 115

Table 169: DBGR1 Register ..................................................................................................... 115

Table 170: DBGR1 Register Bits ............................................................................................. 116

Table 171: DBGR2 Register ..................................................................................................... 116

Table 172: DBGR2 Register Bits ............................................................................................. 116

Table 173: PMUENABLE Register ......................................................................................... 116

Table 174: PMUENABLE Register Bits .................................................................................. 117

Table 175: TPIUCTRL Register ............................................................................................... 117

Table 176: TPIUCTRL Register Bits ....................................................................................... 117

Table 177: CACHECTRL Register Map .................................................................................. 122

Table 178: CACHECFG Register ............................................................................................. 123

Table 179: CACHECFG Register Bits ..................................................................................... 123

Table 180: FLASHCFG Register ............................................................................................. 124

Table 181: FLASHCFG Register Bits ...................................................................................... 124

Table 182: CACHECTRL Register .......................................................................................... 125

Apollo2 Blue Datasheet

DS-A2B-0p2 Page 17 of 536 2017 Ambiq Micro, Inc.

Table 183: CACHECTRL Register Bits ................................................................................... 125

Table 184: NCR0START Register ........................................................................................... 126

Table 185: NCR0START Register Bits .................................................................................... 126

Table 186: NCR0END Register ............................................................................................... 127

Table 187: NCR0END Register Bits ........................................................................................ 127

Table 188: NCR1START Register ........................................................................................... 127

Table 189: NCR1START Register Bits .................................................................................... 127

Table 190: NCR1END Register ............................................................................................... 128

Table 191: NCR1END Register Bits ........................................................................................ 128

Table 192: DMON0 Register .................................................................................................... 128

Table 193: DMON0 Register Bits ............................................................................................ 129

Table 194: DMON1 Register .................................................................................................... 129

Table 195: DMON1 Register Bits ............................................................................................ 129

Table 196: DMON2 Register .................................................................................................... 129

Table 197: DMON2 Register Bits ............................................................................................ 130

Table 198: DMON3 Register .................................................................................................... 130

Table 199: DMON3 Register Bits ............................................................................................ 130

Table 200: IMON0 Register ..................................................................................................... 130

Table 201: IMON0 Register Bits .............................................................................................. 131

Table 202: IMON1 Register ..................................................................................................... 131

Table 203: IMON1 Register Bits .............................................................................................. 131

Table 204: IMON2 Register ..................................................................................................... 131

Table 205: IMON2 Register Bits .............................................................................................. 132

Table 206: IMON3 Register ..................................................................................................... 132

Table 207: IMON3 Register Bits .............................................................................................. 132

Table 208: Operating Modes .................................................................................................... 140

Table 209: Die-to-Die Interconnection Table ........................................................................... 143

Table 210: CMD Register for I2C Operations .......................................................................... 145

Table 211: CMD Register for SPI Operations .......................................................................... 145

Table 212: CMD Register Field Description ............................................................................ 146

Table 213: IOMSTR Register Map .......................................................................................... 160

Table 214: FIFO Register ......................................................................................................... 162

Table 215: FIFO Register Bits .................................................................................................. 162

Table 216: FIFOPTR Register .................................................................................................. 163

Table 217: FIFOPTR Register Bits .......................................................................................... 163

Table 218: TLNGTH Register .................................................................................................. 163

Table 219: TLNGTH Register Bits .......................................................................................... 164

Table 220: FIFOTHR Register ................................................................................................. 164

Table 221: FIFOTHR Register Bits .......................................................................................... 164

Table 222: CLKCFG Register .................................................................................................. 165

Table 223: CLKCFG Register Bits ........................................................................................... 165

Table 224: CMD Register ......................................................................................................... 166

Table 225: CMD Register Bits ................................................................................................. 166

Table 226: CMDRPT Register ................................................................................................. 167

Table 227: CMDRPT Register Bits .......................................................................................... 167

Table 228: STATUS Register ................................................................................................... 167

Apollo2 Blue Datasheet

DS-A2B-0p2 Page 18 of 536 2017 Ambiq Micro, Inc.

Table 229: STATUS Register Bits ........................................................................................... 167

Table 230: CFG Register .......................................................................................................... 168

Table 231: CFG Register Bits ................................................................................................... 168

Table 232: INTEN Register ...................................................................................................... 170

Table 233: INTEN Register Bits .............................................................................................. 170

Table 234: INTSTAT Register ................................................................................................. 171

Table 235: INTSTAT Register Bits .......................................................................................... 171

Table 236: INTCLR Register ................................................................................................... 172

Table 237: INTCLR Register Bits ............................................................................................ 173

Table 238: INTSET Register .................................................................................................... 174

Table 239: INTSET Register Bits ............................................................................................. 174

Table 240: Mapping of Direct Area Access Interrupts and Corresponding REGACCINTSTAT

Bits ............................................................................................................................................. 179

Table 241: I/O Interface Interrupt Control ................................................................................ 182

Table 242: IOSLAVE Register Map ........................................................................................ 190

Table 243: FIFOPTR Register .................................................................................................. 191

Table 244: FIFOPTR Register Bits .......................................................................................... 191

Table 245: FIFOCFG Register ................................................................................................. 191

Table 246: FIFOCFG Register Bits .......................................................................................... 192

Table 247: FIFOTHR Register ................................................................................................. 192

Table 248: FIFOTHR Register Bits .......................................................................................... 192

Table 249: FUPD Register ........................................................................................................ 193

Table 250: FUPD Register Bits ................................................................................................ 193

Table 251: FIFOCTR Register ................................................................................................. 193

Table 252: FIFOCTR Register Bits .......................................................................................... 193

Table 253: FIFOINC Register .................................................................................................. 194

Table 254: FIFOINC Register Bits ........................................................................................... 194

Table 255: CFG Register .......................................................................................................... 194

Table 256: CFG Register Bits ................................................................................................... 195

Table 257: PRENC Register ..................................................................................................... 195

Table 258: PRENC Register Bits .............................................................................................. 196

Table 259: IOINTCTL Register ............................................................................................... 196

Table 260: IOINTCTL Register Bits ........................................................................................ 196

Table 261: GENADD Register ................................................................................................. 197

Table 262: GENADD Register Bits .......................................................................................... 197

Table 263: INTEN Register ...................................................................................................... 197

Table 264: INTEN Register Bits .............................................................................................. 197

Table 265: INTSTAT Register ................................................................................................. 198

Table 266: INTSTAT Register Bits .......................................................................................... 198

Table 267: INTCLR Register ................................................................................................... 199

Table 268: INTCLR Register Bits ............................................................................................ 199

Table 269: INTSET Register .................................................................................................... 200

Table 270: INTSET Register Bits ............................................................................................. 200

Table 271: REGACCINTEN Register ...................................................................................... 201

Table 272: REGACCINTEN Register Bits .............................................................................. 201

Table 273: REGACCINTSTAT Register ................................................................................. 201

Apollo2 Blue Datasheet

DS-A2B-0p2 Page 19 of 536 2017 Ambiq Micro, Inc.

Table 274: REGACCINTSTAT Register Bits .......................................................................... 202

Table 275: REGACCINTCLR Register ................................................................................... 202

Table 276: REGACCINTCLR Register Bits ............................................................................ 202

Table 277: REGACCINTSET Register .................................................................................... 202

Table 278: REGACCINTSET Register Bits ............................................................................ 203

Table 279: HOST_IER Register ............................................................................................... 203

Table 280: HOST_IER Register Bits ........................................................................................ 203

Table 281: HOST_ISR Register ............................................................................................... 204

Table 282: HOST_ISR Register Bits ........................................................................................ 204

Table 283: HOST_WCR Register ............................................................................................ 205

Table 284: HOST_WCR Register Bits ..................................................................................... 205

Table 285: HOST_WCS Register ............................................................................................. 205

Table 286: HOST_WCS Register Bits ..................................................................................... 205

Table 287: FIFOCTRLO Register ............................................................................................ 207

Table 288: FIFOCTRLO Register Bits ..................................................................................... 207

Table 289: FIFOCTRUP Register ............................................................................................ 207

Table 290: FIFOCTRUP Register Bits ..................................................................................... 207

Table 291: FIFO Register ......................................................................................................... 208

Table 292: FIFO Register Bits .................................................................................................. 208

Table 293: PDM Clock Output Reference Table ...................................................................... 211

Table 294: PDM Operating Modes and Data Formats ............................................................. 212

Table 295: Digital Volume Control .......................................................................................... 213

Table 296: LPF Digital Filter Parameters ................................................................................. 214

Table 297: PDM Register Map ................................................................................................. 216

Table 298: PCFG Register ........................................................................................................ 217

Table 299: PCFG Register Bits ................................................................................................ 217

Table 300: VCFG Register ....................................................................................................... 219

Table 301: VCFG Register Bits ................................................................................................ 219

Table 302: FR Register ............................................................................................................. 220

Table 303: FR Register Bits ...................................................................................................... 220

Table 304: FRD Register .......................................................................................................... 221

Table 305: FRD Register Bits ................................................................................................... 221

Table 306: FLUSH Register ..................................................................................................... 221

Table 307: FLUSH Register Bits .............................................................................................. 221

Table 308: FTHR Register ........................................................................................................ 222

Table 309: FTHR Register Bits ................................................................................................ 222

Table 310: INTEN Register ...................................................................................................... 222

Table 311: INTEN Register Bits .............................................................................................. 222

Table 312: INTSTAT Register ................................................................................................. 223

Table 313: INTSTAT Register Bits .......................................................................................... 223

Table 314: INTCLR Register ................................................................................................... 224

Table 315: INTCLR Register Bits ............................................................................................ 224

Table 316: INTSET Register .................................................................................................... 224

Table 317: INTSET Register Bits ............................................................................................. 224

Table 318: Drive Strength Control Bits .................................................................................... 226

Table 319: Apollo2 Blue Pad Function Mapping ..................................................................... 228

Apollo2 Blue Datasheet

DS-A2B-0p2 Page 20 of 536 2017 Ambiq Micro, Inc.

Table 320: ................................................................................................................................ 228

Table 321: Pad Function Color and Symbol Code .................................................................. 229

Table 322: Special Pad Types ................................................................................................... 229

Table 323: I2C Pullup Resistor Selection ................................................................................. 230

Table 324: IO Master 0 I2C Configuration .............................................................................. 233

Table 325: IO Master 1 I2C Configuration .............................................................................. 234

Table 326: IO Master 2 I2C Configuration .............................................................................. 234

Table 327: IO Master 3 I2C Configuration .............................................................................. 235

Table 328: IO Master 4 I2C Configuration .............................................................................. 235

Table 329: IO Master 5 I2C Configuration .............................................................................. 235

Table 330: IO Master 0 4-wire SPI Configuration ................................................................... 235

Table 332: IO Master 1 4-wire SPI Configuration ................................................................... 237

Table 333: IO Master 1 4-wire SPI nCE Configuration ........................................................... 237

Table 331: IO Master 0 4-wire SPI nCE Configuration ........................................................... 237

Table 334: IO Master 2 4-wire SPI Configuration ................................................................... 238

Table 335: IO Master 2 4-wire SPI nCE Configuration ........................................................... 238

Table 336: IO Master 4 4-wire SPI Configuration ................................................................... 239

Table 337: IO Master 4 4-wire SPI nCE Configuration ........................................................... 239

Table 338: IO Master 5 4-wire SPI Configuration ................................................................... 240

Table 339: IO Master 5 4-wire SPI nCE Configuration ........................................................... 240

Table 340: IO Master 0 3-wire SPI Configuration ................................................................... 240

Table 341: IO Master 1 3-wire SPI Configuration ................................................................... 240

Table 342: IO Master 2 3-wire SPI Configuration ................................................................... 241

Table 343: IO Master 3 3-wire SPI Configuration ................................................................... 241

Table 344: IO Master 4 3-wire SPI Configuration ................................................................... 242

Table 345: IO Master 5 3-wire SPI Configuration ................................................................... 242

Table 346: IO Slave I2C Configuration .................................................................................... 242

Table 347: IO Slave 4-wire SPI Configuration ........................................................................ 243

Table 348: IO Slave 3-wire SPI Configuration ........................................................................ 243

Table 349: I2C Loopback ......................................................................................................... 243

Table 350: 3-wire SPI Loopback .............................................................................................. 244

Table 351: 4-wire SPI Loopback .............................................................................................. 244

Table 352: Counter/Timer Pad Configuration .......................................................................... 246

Table 354: UART0 RX Configuration ..................................................................................... 247

Table 355: UART0 RTS Configuration .................................................................................... 247

Table 356: UART0 CTS Configuration .................................................................................... 247

Table 353: UART0 TX Configuration ...................................................................................... 247

Table 359: UART1 RTS Configuration .................................................................................... 249

Table 360: UART1 CTS Configuration .................................................................................... 249

Table 357: UART1 TX Configuration ...................................................................................... 249

Table 358: UART1 RX Configuration ..................................................................................... 249

Table 362: PDM DATA Configuration .................................................................................... 251

Table 363: I2S BCLK Configuration ........................................................................................ 251

Table 364: I2S WCLK Configuration ...................................................................................... 251

Table 365: I2S DAT Configuration ......................................................................................... 251

Table 361: PDM CLK Configuration ....................................................................................... 251

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