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clocked and is determined by the delays associated with the significant critical paths in the
microarchitecture.
For the past decade, the general approach for improving the performance of superscalar
microprocessors has been to build microarchitectures with increasingly complex issue
logic that can boost the IPC factor in the performance equation. The increase in complex-
ity results from a wider microarchitecture, a bigger instruction window, and more complex
issue methods. However, there is a potential problem with continuing this strategy. While
complex issue logic might be able to extract more parallelism, it can easily limit the clock
speed of the microarchitecture. Microarchitectures with more complex issue logic typi-
cally require longer wires and deeper levels of logic to implement, and hence, can require
longer critical paths in the microarchitecture. Thus, there is a danger of squandering the
gains in IPC to a slow clock; resulting in reduced benefits or even no benefit in overall per-
formance. Furthermore, technology trends suggest that wire delays will increasingly dom-
inate total delay as feature sizes are reduced. These factors suggest that straightforward
scaling of current microarchitectures for higher IPCs might not be the most appropriate
approach for delivering higher performance in future. In summary, there is a trade-off
between issue logic complexity, instructions per cycle (IPC), and clock speed that needs to
be carefully examined while designing improved superscalar microarchitectures. This the-
sis examines this trade-off.
The above discussion underscores the need for investigating superscalar microarchitec-
tures that judiciously use hardware complexity for exploiting significant levels of instruc-
tion-level parallelism while permitting a fast clock. We call such microarchitectures
complexity-effective superscalar microarchitectures.
1
These microarchitectures attempt to
maximize the product of IPC and Clock Frequency rather than push the envelope for each
1. While complexity can be variously quantified in terms such as number of transistors, die area,
and power dissipated, in this thesis complexity is measured as the delay of the critical path
through a piece of logic, and the longest path through any of the pipeline stages determines the
clock speed.
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