TLV320AIC3109-Q1：面向汽车应用的低功耗音频编解码器

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TLV320AIC3109-Q1是一款专为汽车应用设计的高性能音频编解码器，它具备严格遵循AEC-Q100标准的特性，确保在极端环境下的可靠性和安全性。该器件的工作温度范围宽广，支持-40°C至+105°C，符合温度等级2的要求，并通过了人体放电模型（HBM）静电放电（ESD）等级2和组件充电模型（CDM）ESD等级C4B的测试，这在汽车电子系统中是至关重要的。这款音频IC的核心功能包括： 1. 单声道音频解码器：它提供了高达102dBA的信噪比，能够处理8kHz至96kHz的高采样率音频信号，支持3D环绕声、低音增强、高音优化、均衡或去加重等音频效果，确保音质的高质量输出。 2. 单声道音频编码器：拥有92dBA信噪比，同样支持8kHz至96kHz的采样率，内置了数字信号处理和噪声滤波技术，有效提升音频质量的同时减少背景噪音。 3. 多通道音频输入接口：设计有四个音频输入引脚，可同时连接多个差分输入和单端输入，适合灵活的音频源接入需求。 4. 高效音频输出：六个音频驱动器支持全差动或单端耳机输出，以及单声道全差动线路输出，能够驱动各种类型的音频负载，且在3.3V的低功耗模拟供电下，仅需14mW就能实现48kHz的播放性能。 5. 超低功耗模式：配备无源模拟旁路，能够在播放状态下提供极低的功耗，节省能源，延长电池寿命，特别适合电池驱动的车载系统。此外，该产品还提供了一系列的技术文档、工具与软件、支持服务以及社区资源，以帮助用户快速上手并解决可能遇到的问题。最后，值得注意的是，文档末尾的重要通知会涵盖产品可用性、保修政策、安全使用注意事项、知识产权声明以及其他相关免责声明，确保用户在实际应用中能全面了解并遵守相关规定。 TLV320AIC3109-Q1是一款理想的汽车音频解决方案，它的设计、性能和特性使得它在音频处理和汽车电子系统中具有很高的竞争力。

ADC

HPCOM

VCM

DAC

Volume

Control

Digital

Filters

AGC

SW-D2

SW-D1

C Serial

Control Bus

Bias ,

Reference

Voltage Supplies

Audio Clock

Generation

HPOUT

LINE2P

LINE2M

SW-R0

SW-R3

SW-R1

SW-R4

RIGHT_LOP

RIGHT_LOM

LINE1P

LINE1M

MIC1P/LINE1P

MIC1M/LINE1M

DIN

DOUT

BCLK

WCLK

AVDD

AVSS

DRVDD

DRVSS

IOVDD

DVDD

DVSS

MICDET

MICBIAS

MCLK

RESET

SCL

SDA

LINE1P

LINE1M

SW-L0

SW-L3

SW-L1

SW-L4

LEFT_LOP

LEFT_LOM

LINE2P

LINE2M

MIC2P/LINE2P

MIC2M/LINE2M

Audio Serial Bus Interface

PGA

0 dB-59.5 dB

0.5-dB Steps

PGA

0 dB-59.5 dB

0.5-dB Steps

TLV320AIC3109-Q1

ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TLV320AIC3109-Q1 is a highly flexible, low-power, mono audio codec with extensive feature integration

intended for automotive applications. Available in a 5-mm × 5-mm, 32-lead VQFN, the device integrates a host of

features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable

applications.

The TLV320AIC3109-Q1 consists of the following blocks:

• Mono audio multi-bit, delta-sigma digital-to-analog converter (DAC): 8 kHz–96 kHz

• Mono audio multi-bit, delta-sigma analog-to-digital converter (ADC): 8 kHz–96 kHz

• Programmable gain amplifier (PGA): 0-dB to 59.5-dB gain

• Programmable digital audio effects processing (bass, treble, midrange, EQ, notch filter, de-emphasis)

• Two differential or two single-ended microphone or line inputs

• One differential or two single-ended headphone drivers

• Two fully differential line output drivers

• Fully programmable PLL

• Headphone, headset jack detection available as a register status bit

7.2 Functional Block Diagram

TLV320AIC3109-Q1

www.ti.com.cn

ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017

7.3 Feature Description

7.3.1 Hardware Reset

The TLV320AIC3109-Q1 requires a hardware reset after power-up for proper operation. After all power supplies

are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not

performed, the TLV320AIC3109-Q1 may not respond properly to register reads or writes.

This device also offers a software reset (page 0, register 1) that can be used by the host to reset all registers on

page 0 and page 1 to their reset values. In cases where changes are needed only for routing or volume-control

registers, these changes can be accomplished by writing directly to the appropriate registers rather than using

the software or hardware reset.

In cases where the ESD events generate a device reset, a minimum 1-nF capacitor is recommended to be

connected between the RESET pin and DVSS. This capacitor avoids ESD events that can place the codec in

default state.

7.3.2 Digital Audio Data Serial Interface

Audio data are transferred between the host processor and the TLV320AIC3109-Q1 via the digital audio data

serial interface. The audio bus of the TLV320AIC3109-Q1 can be configured for left- or right-justified, I

S, DSP,

or TDM modes of operation, where communication with standard PCM interfaces is supported within TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word

clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode for flexible

connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and can be programmed as either a pulse or

a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling

frequency.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master

mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In

continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are

generated, so in general the number of bit clocks per frame is two times the data width. For example, if the data

width is chosen as 16 bits, then 32-bit clocks are generated per frame. If the bit clock signal in master mode is to

be used by a PLL in another device, then the 16-bit or 32-bit data-width selections are recommended be used.

These cases result in a low-jitter bit clock signal being generated, with frequencies of 32 f

or 64 f

. For a 20-bit

and 24-bit data width in master mode, the bit clocks generated in each frame are not all of equal period because

the device does not have a clean 40-f

or 48-f

clock signal readily available. The average frequency of the bit

clock signal is still accurate in these cases (40 f

or 48 f

), but the resulting clock signal has higher jitter than in

the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.

The TLV320AIC3109-Q1 further includes programmability to place the DOUT line in the high-impedance state

during all bit clocks when valid data are not being sent. By combining this capability with the ability to program at

what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting

in multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down when configured in master mode, the pins

associated with the interface are put into a high-impedance state.

The following subsections describe the supported data interface protocols. These protocols can be used for left-

and right-channel applications. Only one of the two possible channels can be selected because the

TLV320AIC3109-Q1 is a mono audio codec. Only the left channel is valid for DOUT (output data). For DIN (input

data), valid data can be selected with bits 4 and 3 of register 7, page 0.

N–1

1N–1N–2

N–2

Right-ChannelData

Left-ChannelData

••••

•••• ••

DSP Mode

Left-JustifiedMode

Offset

Offset Offset

T0153-01

WordClock

BitClock

DataIn/Out

TLV320AIC3109-Q1

ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017

www.ti.com.cn

Feature Description (接接下下页页)

7.3.2.5 TDM Data Transfer

Time-division multiplexed data transfer can be realized in any of the left-justified transfer modes if the 256-clock

bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By

changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the

serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks

except when valid data is being put onto the bus. This format allows other codecs to be programmed with

different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the

codec simply ignores data on the bus except when expected based on the programmed offset.

The location of the data when an offset is programmed is different depending on what transfer mode is selected.

In DSP mode, both the left and right channels of data are transferred immediately adjacent to each other in the

frame. This configuration differs from left-justified mode, where the left- and right-channel data are always a half-

frame apart in each frame. In this case, when the offset is programmed from zero to some higher value, both the

left- and right-channel data move across the frame, but still stay a full half-frame apart from each other. 图 16

shows the TDM transfer for DSP mode and left-justified mode.

图图 16. DSP Mode and Left-Justified Mode, Showing the

Effect of a Programmed Data-Word Offset

7.3.3 Audio Data Converters

The TLV320AIC3109-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz,

16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at

different sampling rates in various combinations, as described in this section.

The data converters are based on the concept of an f

S(ref)

rate that is used internal to the device, and is related to

the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f

S(ref)

is either

44.1 kHz or 48 kHz, although f

S(ref)

can realistically be set over a wider range of rates up to 53 kHz, with

additional restrictions if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and

also to enable high-quality playback of low-sampling-rate data without high-frequency audible noise being

generated.

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