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0HAL编号:tel-035452120https://theses.hal.science/tel-035452120提交日期:2022年1月27日0HAL是一个多学科开放获取档案库,用于存储和传播科学研究文献,无论其是否发表。这些文献可以来自法国或国外的教育和研究机构,也可以来自公共或私人研究中心。0HAL多学科开放获取档案库旨在存储和传播法国或国外教育和研究机构、公共或私人实验室发表或未发表的研究级科学文献。0Nanvix:一种适用于轻量级多核处理器的分布式操作系统0Pedro Henrique Penna0引用该版本:0Pedro Henrique Penna.Nanvix:一种适用于轻量级多核处理器的分布式操作系统。嵌入式系统。格勒诺布尔阿尔卑斯大学[2020-..];巴西米纳斯吉拉斯天主教大学(巴西),2021年。英文。NNT:2021GRALM027。tel-03545212 0博士论文0获得学位:0格勒诺布尔阿尔卑斯大学博士学位0作为格勒诺布尔阿尔卑斯大学和巴西米纳斯吉拉斯天主教大学的合作项目的一部分准备的0专业:计算机科学0部长令:2005年1月6日-2016年5月25日0由Pedro Henrique DE MELLO MORADOPENNA提交0导师:Jean-François MÉHAUT和Henrique FREITAS0在格勒诺布尔计算机实验室内准备0在数学、科学和信息技术学院的博士学位学科中0Nanvix:一种适用于轻量级多核处理器的分布式操作系统0博士论文于2021年9月23日公开答辩,答辩委员会成员如下:0Abdoulaye GAMATIÉ研究主任,CNRS/LIRMM,主席 PierreSENS教授,巴黎索邦大学,评审员 RodolfoAZEVEDO教授,坎皮纳斯大学,评审员 Benoît DINECHIN工程师博士,KalrayInc,考官 François BROQUEDIS讲师,格勒诺布尔阿尔卑斯大学,考官 MárcioCASTRO副教授,圣卡塔琳娜联邦大学,考官 Carlos AugustoMARTINS教授,巴西米纳斯吉拉斯天主教大学,特邀嘉宾0巴西米纳斯吉拉斯天主教大学计算机科学研究生项目0Pedro Henrique de Mello Morado Penna0NANVIX:一种适用于轻量级多核处理器的分布式操作系统0贝洛奥里藏特2021年0Pedro Henrique de Mello Morado Penna0NANVIX:一种适用于轻量级多核处理器的分布式操作系统0作为获得计算机科学博士学位的部分要求,博士论文提交给巴西米纳斯吉拉斯天主教大学计算机科学研究生项目。0导师:Prof. Dr. Henrique Cota de Freitas(PUC Minas)0导师:Prof. Dr. Jean-François Méhaut(UGA)0贝洛奥里藏特2021年0Pedro Henrique de Mello Morado Penna0NANVIX:一种适用于轻量级多核处理器的分布式操作系统0作为获得计算机科学博士学位的部分要求,博士论文提交给巴西米纳斯吉拉斯天主教大学计算机科学研究生项目。0Prof. Dr. Jean-François Méhaut – UGA(导师)0Prof. Dr. Henrique Freitas – PUC Minas(导师)0Prof. Dr. Abdoulaye Gamatié – LIRMM(考试委员会)0Pierre Sens教授 - Sorbonne Université(考试委员会)0Rodolfo Azevedo教授 - UNICAMP(考试委员会)0Benoît Dinechin博士 - Kalray Inc(考试委员会)0Carlos Augusto Martins教授 - PUC Minas(考试委员会)0François Broquedis教授 - UGA(考试委员会)0Márcio Castro教授 - UFSC(考试委员会)0贝洛奥里藏特2021Keywords: Distributed Operating Systems. Lightweight Manycore Processors.0摘要0轻量级Manycore(LWManycore)处理器的引入旨在提供性能可扩展性和低功耗。为了解决前者,它们依赖于特定的架构特性,如分布式内存架构和丰富的网络-0芯片(NoC)。为了实现低功耗,它们采用简单的低功耗多指令多数据(MIMD)核心构建,它们具有基于刮板内存(SPM)的内存系统,并通过具有不同能力的核心利用异构性。这些处理器的一些在工业上取得成功的例子是Kalray MPPA-256、PULP0和申威SW26010。虽然这一独特的架构特性为LW Manycore提供了0性能可扩展性和能源效率,它们还在软件方面引入了多个挑战0可编程性和可移植性。首先,高密度电路集成将暗硅变为现实。其次,分布式内存架构要求显式获取/0从远程内存加载到本地内存。第三,少量的芯片上内存迫使0软件将其工作数据集分成块并决定哪些块应该保留0本地内存,第四,芯片上的互连使软件工程师采用消息传递编程模型。最后,芯片上的0异构性使得应用程序的部署变得复杂。解决这些挑战的一种方法是通过操作系统(OS)。这种类型的解决方案旨在桥接0通过暴露丰富的抽象和编程接口,以及高级编程接口,来揭示架构的复杂性0如资源分配、共享和复用。不幸的是,现有的操作系统在解决0为了充分解决LWManycore中的可编程性和可移植性挑战,因为它们不是为了应对这些处理器的架构特性而设计的。在这种情况下,这项工作的主要目标是提出一种新颖的LWManycore操作系统,专门应对这些未解决的挑战。这项工作的主要贡献是一种分布式操作系统,它推进了LWManycore处理器中的资源管理。一方面,从科学的角度来看,这个主要贡献可以展开为三个具体的贡献。首先,一个全面的硬件抽象层(HAL),使得开发和0部署完整功能的LW Manycore操作系统更加容易,同时也实现了0跨多个这些处理器的操作系统。其次,一种丰富的内存管理方法,0基于分布式分页系统(DPS)。这是我们为LWManycore设计的一种新颖的系统级解决方案,用于管理内存。第三,一种轻量级通信设施,用于管理芯片上的互连并通过硬件通道复用暴露原语。另一方面,作为技术贡献,这项工作引入了Nanvix。这是一个具体的0LWManycore处理器的操作系统的实现,其中包含上述的科学进展。Nanvix支持多种架构(Bostan、x86、OpenRISC、ARMv8和RISC-V),在裸机处理器上运行,暴露丰富的抽象和高级编程接口。RESUMOProcessadores LW Manycore foram introduzidos para fornecer escalabilidade de desempenho aum baixo consumo de energia. Para abordar o primeiro aspecto, eles contam com característicasarquiteturais específicas, como uma arquitetura de memória distribuída e um rede-em-chip. Paraatingir baixo consumo de energia, esses processadores são construídos com núcleos simplese de baixo consumo de energia, têm um sistema de memória baseado em SPM e exploramheterogeneidade. Alguns exemplos de sucesso desses processadores são o Kalray MPPA-256, oPULP e o Sunway SW26010. Embora este conjunto único de recursos arquiteturais concedaa LW Manycore desempenho escalabilidade e eficiência energética, eles também apresentamvários desafios na programação e portabilidade do software. Primeiro, a integração do circuitode alta densidade transforma o problema de dark silicon em realidade. Em segundo lugar,a arquitetura de memória distribuída requer que os dados sejam explicitamente buscados /descarregados de memórias remotas para memórias locais. Terceiro, a pequena quantidade dememória on-chip força o software a particionar seu conjunto de dados de trabalho em blocos edecidir qual deles deve ser mantido local e deve ser descarregado para a memória remota. Quarto,a interconexão on-chip convida engenheiros de software a abraçar um modelo de programação depassagem de mensagens. Finalmente, a heterogeneidade no chip torna complexa a implantação deaplicações. Uma abordagem para enfrentar esses desafios é por meio de um sistema operacional(SO). Esse tipo de solução anseia por superar as complexidades de uma arquitetura, por exporabstrações ricas e interfaces de programação, bem como manipular alocação, compartilhamento emultiplexação de recursos. Infelizmente, os sistemas existentes lutam para resolver totalmente aprogramabilidade e desafios de portabilidade em LW Manycore, porque eles não foram projetadospara lidar com características arquitetônicas desses processadores. Nesse contexto, o principalobjetivo deste trabalho se resume em propor um SO para LW Manycore que lida especificamentecom esses desafios. A principal contribuição deste trabalho é um SO distribuído que avança ogerenciamento de recursos em processadores LW Manycore. Por um lado, do ponto de vistacientífico, esta contribuição principal pode ser desdobrada em três contribuições específicas. Emprimeiro lugar, uma HAL abrangente que torna o desenvolvimento e implantação de um SOtotalmente caracterizado para LW Manycore mais fácil, bem como permite a portabilidade deum SO em vários desses processadores. Em segundo lugar, uma abordagem de gerenciamentode memória rica que se baseia em DPS,uma nova solução em nível de sistema que criamospara gerenciar a memória de um LW Manycore. Terceiro, uma facilidade de comunicaçãoleve que gerencia o on-chip interconecta e expõe primitivas com multiplexação de canal dehardware. Por outro lado, como contribuição técnica, este trabalho apresenta o Nanvix. Esta éuma implementação concreta de um processador SO para LW Manycore que apresenta os avançoscientíficos mencionados. Nanvix suporta múltiplos arquiteturas é executado em processadoresbaremetal, expõe abstrações ricas e programação de alto nível interfaces.Palavras-chave: Sistemas Operacionais Distribuídos. Processadores Manycore leves.LIST OF FIGURESFigure 1 – An extended taxonomy for single-chip manycore architectures. . . . . . . .24Figure 2 – Manycore accelerators.. . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 3 – Manycore processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 4 – A LW Manycore processor with 67 cores.. . . . . . . . . . . . . . . . . .27Figure 5 – A possible architecture for an OS. . . . . . . . . . . . . . . . . . . . . . . .30Figure 6 – Popular architectures for an OS. . . . . . . . . . . . . . . . . . . . . . . . .31Figure 7 – Memory partitioning techniques. . . . . . . . . . . . . . . . . . . . . . . .32Figure 8 – Memory allocation techniques. . . . . . . . . . . . . . . . . . . . . . . . .33Figure 9 – Memory virtualization techniques.. . . . . . . . . . . . . . . . . . . . . .35Figure 10 – States diagram for a process.. . . . . . . . . . . . . . . . . . . . . . . . .38Figure 11 – Possible organizations for a file. . . . . . . . . . . . . . . . . . . . . . . . .44Figure 12 – File allocation schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 13 – A possible layout for a file system. . . . . . . . . . . . . . . . . . . . . . .46Figure 14 – Structure of a directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Figure 15 – Architectures for distributed OSes. . . . . . . . . . . . . . . . . . . . . . .47Figure 16 – Communication mechanisms for distributed systems.. . . . . . . . . . . .48Figure 17 – Replica placement in a distribute system. . . . . . . . . . . . . . . . . . . .53Figure 18 – Operating systems for single-chip manycore architectures. . . . . . . . . . .67Figure 19 – A structural overview of Nanvix. . . . . . . . . . . . . . . . . . . . . . . .70Figure 20 – Structural overview of the HAL of Nanvix. . . . . . . . . . . . . . . . . . .72Figure 21 – Structural overview of the Nanvix microkernel.. . . . . . . . . . . . . . .76Figure 22 – Memory system module.. . . . . . . . . . . . . . . . . . . . . . . . . . .77Figure 23 – Execution flow of sync abstraction. . . . . . . . . . . . . . . . . . . . . . .81Figure 24 – Execution flow of mailbox abstraction (N:1). . . . . . . . . . . . . . . . . .82Figure 25 – Execution flow of portal abstraction (1:1). . . . . . . . . . . . . . . . . . .82Figure 26 – Services of Nanvix running on a lightweight manycore processor. . . . . . .84Figure 27 – Process spawn in Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . . . .86Figure 28 – States of a process in Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . .87Figure 29 – Process migration in Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . .88Figure 30 – Shared memory region creation in Nanvix. . . . . . . . . . . . . . . . . . .92Figure 31 – Remote page fetch in Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . .93Figure 32 – Virtual file system of Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . .94Figure 33 – Architectural overview of the MPPA-256 LW Manycore processor. . . . . . 105Figure 34 – Mailbox latency when varying message size. . . . . . . . . . . . . . . . . . 109Figure 35 – Mailbox throughput for fixed-size messages. . . . . . . . . . . . . . . . . . 110Figure 36 – Sync latency scalability for synchronization signals. . . . . . . . . . . . . . 110Figure 37 – Portal bandwidth scalability for dense data transfers. . . . . . . . . . . . . . 111Figure 38 – Mailbox and portal throughput when varying transfer size. . . . . . . . . . . 112Figure 39 – Uncached read/write bandwidth.. . . . . . . . . . . . . . . . . . . . . . . 114Figure 40 – Cached read/write bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . 115Figure 41 – Execution breakthrough for local kernel calls.. . . . . . . . . . . . . . . . 117Figure 42 – Execution breakthrough for remote kernel calls. . . . . . . . . . . . . . . . 118Figure 43 – Performance scalability for creating and terminating threads.. . . . . . . . 119Figure 44 – Execution efficiency for the knoise Benchmark. . . . . . . . . . . . . . . . 120Figure 45 – Performance for system utilities.. . . . . . . . . . . . . . . . . . . . . . . 121Figure 46 – Performance of Nanvix under heavy-load.. . . . . . . . . . . . . . . . . . 122Figure 47 – Execution times for fn, gf and km. . . . . . . . . . . . . . . . . . . . . . . 123Figure 48 – Power consumption for km when varying the number of clusters/problem sizes.124Figure 49 – Energy consumption for fn, gf and km. . . . . . . . . . . . . . . . . . . . . 124Figure 50 – Architectural overview of the MPPA-256 LW Manycore processor. . . . . . 147Figure 51 – Uma taxonomia estendida para arquiteturas manycore de chip único. . . . . 155Figure 52 – Uma possível arquitetura para um sistema operacional.. . . . . . . . . . . 158Figure 53 – Arquiteturas para sistemas operacionais distribuídos. . . . . . . . . . . . . . 159Figure 54 – Sistemas operacionais para arquiteturas multicore de chip único.. . . . . . 161Figure 55 – Uma visão geral estrutural de Nanvix.. . . . . . . . . . . . . . . . . . . . 162Figure 56 – Visão geral da arquitetura do processador MPPA-256 LW Manycore. . . . . 165Figure 57 – Desempenho para utilitários do sistema.. . . . . . . . . . . . . . . . . . . 170Figure 58 – Desempenho do Nanvix sob carga pesada. . . . . . . . . . . . . . . . . . . 171Figure 59 – Une taxonomie étendue pour les architectures multicœurs à puce unique. . . 178Figure 60 – Une architecture possible pour un OS.. . . . . . . . . . . . . . . . . . . . 182Figure 61 – Architecture pour les systèmes d’exploitation distribués. . . . . . . . . . . . 182Figure 62 – Systèmes d’exploitation pour architectures multicœurs à puce unique. . . . . 184Figure 63 – Un aperçu structurel de Nanvix. . . . . . . . . . . . . . . . . . . . . . . . . 185Figure 64 – Présentation architecturale du processeur MPPA-256 LW Manycore. . . . . 188Figure 65 – Performance pour les utilitaires système. . . . . . . . . . . . . . . . . . . . 193Figure 66 – Performance de Nanvix sous forte charge.. . . . . . . . . . . . . . . . . . 194LIST OF TABLESTable 2 – List of IPC abstractions and primitives commonly found in OSes.. . . . . .42Table 4 – Distributed OSes for network environments vs LW Manycore. . . . . . . . .58Table 6 – Interface exposed by the Cluster Abstraction Layer. . . . . . . . . . . . . . .74Table 8 – Experimental programs used for assessing Nanvix . . . . . . . . . . . . . . . 102Table 9 – Performance of memory management protocols.. . . . . . . . . . . . . . . 1160表1-流行调度算法的概要。. . . . . . . . . . . . . . . . . . . 380表3-文件的常见操作。. . . . . . . . . . . . . . . . . . . . . . . . . . 430表5-核心抽象层暴露的接口。. . . . . . . . . . . . . . . . 730表7-处理器抽象层暴露的接口。. . . . . . . . . . . . . . 740表10-流程管理协议的性能。. . . . . . . . . . . . . . . . . 120 表11-OpTiMSoC中核心的设计空间。. .. . . . . . . . . . . . . . . . . . . . 149 表12-用于评估Nanvix的实验性程序。. . . . . . . . . . . . . . 164表13-用于评估Nanvix的实验性程序。. . . . . . . . . . . . . . 187TABLE OF CONTENTS1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171.1Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181.2Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191.3Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.4Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.5Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212BACKGROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232.1Single-Chip Manycore Processors . . . . . . . . . . . . . . . . . . . . . .232.1.1Manycore Accelerators. . . . . . . . . . . . . . . . . . . . . . . . . . . .242.1.2Manycore Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . .252.1.3Lightweight Manycore Processors . . . . . . . . . . . . . . . . . . . . . . .262.2Runtime Systems for Parallel and Distributed Programming . . . . . . .282.3Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292.3.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292.3.2Operating System Construction . . . . . . . . . . . . . . . . . . . . . . . .302.3.3Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322.3.4Process Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . .372.3.5File System Management . . . . . . . . . . . . . . . . . . . . . . . . . . .422.4Distributed Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . .462.4.1System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472.4.2Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482.4.3Coordination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492.4.4Replica Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . .532.4.5Data Consistency.
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