always @ (posedge clk or posedge rst) begin if (rst) begin seg = 4'b0000; end else Error (10170): Verilog HDL syntax error at keshe11.v(84) near text "always"; expecting ";", or "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement这个错误怎么改

这个错误是因为 always 语句中的语法有问题。你需要在 always 后面添加 @(*) 或者 @ (posedge clk) 来指定触发条件。

例如：

always @(*) begin
    if (rst) begin
        seg = 4'b0000;
    end else begin
        // your code here
    end
end

或者

always @(posedge clk) begin
    if (rst) begin
        seg = 4'b0000;
    end else begin
        // your code here
    end
end

注意：以上代码只是示例，你需要将其中的代码替换成你自己的代码。同时，还需要确保你的代码没有其他的语法错误。