这是一道电路设计题目，需要设计一个计分系统来记录比赛中黄队和红队的得分，并在比赛结束后显示总分。题目要求如下： （1）拨动开关sw1为H，开始比赛。八位七数码管从左数第1、2位显示黄 队分数，第7、8位显示红队分数。开始比赛时同时显示为00。按下键盘*1代表 黄队加1分；按下键盘*2代表黄队加2分；按下键盘*3代表黄队加3分；同时 对应的黄色led灯亮。按下键盘#1代表红队加1分；按下键盘#2代表红队加2 分；按下键盘#3代表红队加3分；同时对应的红色led灯亮。 （2）拨动开关sw1为L，结束比赛。总分大的队伍对应颜色的led灯闪烁 （闪烁频率为4Hz） （3）外部输入脉冲信号频率为50mhz； 请帮我完成下列问题 1、按照现代数字系统的Top-Down模块化设计方法，提出整体设计方案，并 进行正确的功能划分，分别提出并实现模块化子系统的设计方案。 2、完成系统的顶层设计、各子系统的模块化设计。分别完成各个基于Verilog 语言实现的子模块的逻辑功能仿真。最后对顶层设计进行功能仿真。

1、整体设计方案：

整体设计分为三个子系统：计分系统、七数码管显示、LED闪烁控制。其中，计分系统用于记录黄队和红队的得分，七数码管显示用于显示当前得分，LED闪烁控制用于结束比赛后控制得分高的队伍对应颜色的LED灯闪烁。具体模块化子系统的设计方案如下：

计分系统：
- 记录黄队得分和红队得分
- 接收键盘输入，根据输入控制得分增加
- 控制对应的黄色LED或红色LED亮起

七数码管显示：
- 接收黄队得分和红队得分
- 将分数转换成BCD码
- 控制七数码管显示分数

LED闪烁控制：
- 接收黄队得分和红队得分
- 比较总分大小，确定哪一支队伍得分高
- 控制对应的LED闪烁

2、各子系统的模块化设计：

计分系统：

module score_system(clk, rst, sw, key, yellow_score, red_score, yellow_led, red_led);
    input clk, rst, sw, key;
    output reg [7:0] yellow_score, red_score;
    output reg yellow_led, red_led;
    
    always @(posedge clk) begin
        if(rst) begin
            yellow_score <= 8'b00000000;
            red_score <= 8'b00000000;
            yellow_led <= 1'b0;
            red_led <= 1'b0;
        end else if(sw) begin
            case(key)
                3'b001: begin //黄队加1分
                    yellow_score <= yellow_score + 1;
                    yellow_led <= 1'b1;
                end
                3'b010: begin //黄队加2分
                    yellow_score <= yellow_score + 2;
                    yellow_led <= 1'b1;
                end
                3'b011: begin //黄队加3分
                    yellow_score <= yellow_score + 3;
                    yellow_led <= 1'b1;
                end
                3'b100: begin //红队加1分
                    red_score <= red_score + 1;
                    red_led <= 1'b1;
                end
                3'b101: begin //红队加2分
                    red_score <= red_score + 2;
                    red_led <= 1'b1;
                end
                3'b110: begin //红队加3分
                    red_score <= red_score + 3;
                    red_led <= 1'b1;
                end
                default: begin
                    yellow_led <= 1'b0;
                    red_led <= 1'b0;
                end
            endcase
        end
    end
endmodule

七数码管显示：

module seven_segment(clk, rst, score, seg);
    input clk, rst;
    input [7:0] score;
    output reg [6:0] seg;
    
    always @(posedge clk) begin
        if(rst) begin
            seg <= 7'b1111111;
        end else begin
            case(score)
                8'b00000000: seg <= 7'b1000000; //0
                8'b00000001: seg <= 7'b1111001; //1
                8'b00000010: seg <= 7'b0100100; //2
                8'b00000011: seg <= 7'b0110000; //3
                8'b00000100: seg <= 7'b0011001; //4
                8'b00000101: seg <= 7'b0010010; //5
                8'b00000110: seg <= 7'b0000010; //6
                8'b00000111: seg <= 7'b1111000; //7
                8'b00001000: seg <= 7'b0000000; //8
                8'b00001001: seg <= 7'b0010000; //9
                default: seg <= 7'b1111111;
            endcase
        end
    end
endmodule

LED闪烁控制：

module led_blink(clk, rst, yellow_score, red_score, yellow_led, red_led);
    input clk, rst;
    input [7:0] yellow_score, red_score;
    input yellow_led, red_led;
    
    reg yellow_blink, red_blink;
    reg [31:0] cnt;
    always @(posedge clk) begin
        if(rst) begin
            yellow_blink <= 1'b0;
            red_blink <= 1'b0;
            cnt <= 32'd0;
        end else begin
            if(yellow_score > red_score) begin
                yellow_blink <= 1'b1;
                red_blink <= 1'b0;
            end else if(yellow_score < red_score) begin
                yellow_blink <= 1'b0;
                red_blink <= 1'b1;
            end else begin
                yellow_blink <= 1'b0;
                red_blink <= 1'b0;
            end
            
            if(cnt == 50000000) begin
                cnt <= 32'd0;
            end else begin
                cnt <= cnt + 1;
            end
        end
    end
    
    assign yellow_led = yellow_blink && (cnt[24]);
    assign red_led = red_blink && (cnt[24]);
endmodule

顶层设计：

module top(clk, rst, sw, key, yellow_score, red_score, seg, yellow_led, red_led);
    input clk, rst, sw, key;
    output [7:0] yellow_score, red_score;
    output [6:0] seg;
    output yellow_led, red_led;
    
    wire [7:0] score1, score2;
    wire [6:0] seg1, seg2;
    wire led1, led2;
    
    score_system score(clk, rst, sw, key, score1, score2, led1, led2);
    seven_segment seg_yellow(clk, rst, score1, seg1);
    seven_segment seg_red(clk, rst, score2, seg2);
    led_blink blink(clk, rst, score1, score2, led1, led2);
    
    assign yellow_score = score1;
    assign red_score = score2;
    assign seg = {seg2, seg1};
    assign yellow_led = led1;
    assign red_led = led2;
endmodule

功能仿真：

使用Verilog仿真工具对顶层设计进行功能仿真，检查各个子系统是否正常工作。