用Verilog代码写一个4-16线译码器
时间: 2024-05-03 12:16:50 浏览: 26
下面是一个4-16线译码器的Verilog代码示例:
```
module decoder_4x16(input [3:0] addr, output reg [15:0] out);
always @ (addr) begin
case (addr)
4'b0000: out <= 16'b0000000000000001;
4'b0001: out <= 16'b0000000000000010;
4'b0010: out <= 16'b0000000000000100;
4'b0011: out <= 16'b0000000000001000;
4'b0100: out <= 16'b0000000000010000;
4'b0101: out <= 16'b0000000000100000;
4'b0110: out <= 16'b0000000001000000;
4'b0111: out <= 16'b0000000010000000;
4'b1000: out <= 16'b0000000100000000;
4'b1001: out <= 16'b0000001000000000;
4'b1010: out <= 16'b0000010000000000;
4'b1011: out <= 16'b0000100000000000;
4'b1100: out <= 16'b0001000000000000;
4'b1101: out <= 16'b0010000000000000;
4'b1110: out <= 16'b0100000000000000;
4'b1111: out <= 16'b1000000000000000;
endcase
end
endmodule
```
这个译码器的输入为4位地址,输出为16位数据。当输入的地址为0000时,输出的数据为0000000000000001,当输入的地址为0001时,输出的数据为0000000000000010,以此类推,直到输入的地址为1111时,输出的数据为1000000000000000。这个译码器可以根据输入的地址选择其中一个输出。