给出DVI接口的Verilog程序和其对应的testbench程序，一共两个程序分开来

以下是DVI接口的Verilog程序：

module dvi_interface (
    input clk,
    input rst,
    input [7:0] red,
    input [7:0] green,
    input [7:0] blue,
    output hsync,
    output vsync,
    output [3:0] pixel_clk
);

parameter H_SYNC_CYCLES = 96;
parameter H_PIXELS = 640;
parameter H_FRONT_PORCH = 16;
parameter H_BACK_PORCH = 48;
parameter V_SYNC_LINES = 2;
parameter V_PIXELS = 480;
parameter V_FRONT_PORCH = 11;
parameter V_BACK_PORCH = 31;

reg [11:0] h_count = 0;
reg [9:0] v_count = 0;
reg [1:0] h_sync_count = 0;
reg [3:0] pixel_count = 0;
reg [1:0] v_sync_count = 0;

reg h_sync = 1'b0;
reg vsync = 1'b0;
reg [3:0] pixel_clk = 4'b0000;

always @(posedge clk) begin
    if (rst) begin
        h_count <= 0;
        v_count <= 0;
        h_sync_count <= 0;
        pixel_count <= 0;
        h_sync <= 1'b0;
        vsync <= 1'b0;
        pixel_clk <= 4'b0000;
    end
    else begin
        // Horizontal counter
        if (h_count == H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH + H_BACK_PORCH - 1)
            h_count <= 0;
        else
            h_count <= h_count + 1;

        // Vertical counter
        if (h_count == H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH + H_BACK_PORCH - 1) begin
            if (v_count == V_SYNC_LINES + V_PIXELS + V_FRONT_PORCH + V_BACK_PORCH - 1)
                v_count <= 0;
            else
                v_count <= v_count + 1;
        end

        // Pixel clock
        if (pixel_count == 3)
            pixel_count <= 0;
        else
            pixel_count <= pixel_count + 1;

        // Horizontal sync
        if (h_sync_count == H_SYNC_CYCLES - 1) begin
            h_sync_count <= 0;
            h_sync <= 1'b1;
        end
        else if (h_sync_count == H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH + H_BACK_PORCH - 1) begin
            h_sync_count <= 0;
            h_sync <= 1'b0;
        end
        else
            h_sync_count <= h_sync_count + 1;

        // Vertical sync
        if (v_sync_count == V_SYNC_LINES - 1) begin
            v_sync_count <= 0;
            vsync <= 1'b1;
        end
        else if (v_sync_count == V_SYNC_LINES + V_PIXELS + V_FRONT_PORCH + V_BACK_PORCH - 1) begin
            v_sync_count <= 0;
            vsync <= 1'b0;
        end
        else
            v_sync_count <= v_sync_count + 1;

        // Pixel clock
        if (h_count < H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH)
            pixel_clk <= {4'b0001, {4{pixel_count[1]}}};
        else
            pixel_clk <= 4'b0000;
    end
end

// RGB output
assign red = (h_count < H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH) ? 8'd255 : 8'd0;
assign green = (h_count < H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH) ? 8'd255 : 8'd0;
assign blue = (h_count < H_SYNC_CYCLES + H_PIXELS + H_FRONT_PORCH) ? 8'd255 : 8'd0;

endmodule

以下是DVI接口的testbench程序：

module dvi_interface_tb;

reg clk;
reg rst;
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
wire hsync;
wire vsync;
wire [3:0] pixel_clk;

dvi_interface dut (
    .clk(clk),
    .rst(rst),
    .red(red),
    .green(green),
    .blue(blue),
    .hsync(hsync),
    .vsync(vsync),
    .pixel_clk(pixel_clk)
);

initial begin
    clk <= 1'b0;
    rst <= 1'b1;
    #10 rst <= 1'b0;
end

always #5 clk <= ~clk;

initial begin
    $dumpfile("dvi_interface_tb.vcd");
    $dumpvars(0, dvi_interface_tb);
    #100000 $finish;
end

endmodule