用Verilog HDL设计系统,按照(3’b000->3’ b001->3’ b011->3’b111->3’b101->3b100->3’b110->3'b010->3’b000）b010->3’b000）规律工作的计数器，对输入时钟信号进行计数。要习1、系统可以异步复位，同步使能2、用四位一体数码管对计数值以二讲制形式讲行实时、同步显示

好的，这是一个计数器的Verilog HDL设计，满足您的需求：

module counter(
  input clk, //输入时钟信号
  input rst, //异步复位信号
  input en,  //同步使能信号
  output reg [3:0] seg //四位一体数码管输出
);

reg [2:0] count; //计数器寄存器
reg [2:0] next_count; //下一个计数器值

//计数器状态转移规律
always @ (posedge clk or posedge rst) begin
  if (rst) begin
    count <= 3'b000; //复位时计数器清零
  end else if (en) begin
    count <= next_count; //使能时根据规律更新计数器值
  end
end

//根据规律生成下一个计数器值
always @ (count) begin
  case (count)
    3'b000: next_count = 3'b001;
    3'b001: next_count = 3'b011;
    3'b011: next_count = 3'b111;
    3'b111: next_count = 3'b101;
    3'b101: next_count = 3'b100;
    3'b100: next_count = 3'b110;
    3'b110: next_count = 3'b010;
    3'b010: next_count = 3'b000;
    default: next_count = 3'b000;
  endcase
end

//将计数器值转换为二进制数并输出到数码管上
always @ (count) begin
  case (count)
    3'b000: seg = 4'b0000;
    3'b001: seg = 4'b0001;
    3'b010: seg = 4'b0010;
    3'b011: seg = 4'b0011;
    3'b100: seg = 4'b0100;
    3'b101: seg = 4'b0101;
    3'b110: seg = 4'b0110;
    3'b111: seg = 4'b0111;
    default: seg = 4'b0000;
  endcase
end

endmodule

该计数器模块包括异步复位、同步使能和计数器状态转移三个部分。在计数器状态转移部分，使用了case语句实现了计数器状态的转移。在计数器值转换部分，同样使用了case语句实现了计数器值到二进制数的转换，并将结果输出到四位一体数码管上进行实时、同步显示。

希望这个Verilog HDL设计能够满足您的需求。