为这段代码加注释module sy2(a,b,c,d,e,f,g,sel,clk,en); output a,b,c,d,e,f,g; output [7:0]sel; input [7:0] en; input clk; reg a,b,c,d,e,f,g; reg [7:0] sel; reg clk_reg; reg [8:0] count; reg [2:0] state; parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3, s4=3'd4,s5=3'd5,s6=3'd6,s7=3'd7; always@(posedge clk) if(count==9'd400) begin clk_reg<=~clk_reg; count<=9'd0; end else count<=count+9'd1; always@(posedge clk_reg) begin case(state) s0: begin if(en[7]) begin sel<=8'b0111_1111; {a,b,c,d,e,f,g}<=7'b1101101; end else sel<=8'b1111_1111; state<=s1; end s1: begin if(en[6]) begin sel<=8'b1011_1111; {a,b,c,d,e,f,g}<=7'b1111110; end else sel<=8'b1111_1111; state<=s2; end s2: begin if(en[5]) begin sel<=8'b1101_1111; {a,b,c,d,e,f,g}<=7'b1111110; end else sel<=8'b1111_1111; state<=s3; end s3: begin if(en[4]) begin sel<=8'b1110_1111; {a,b,c,d,e,f,g}<=7'b1101101; end else sel<=8'b1111_1111; state<=s4; end s4: begin if(en[3]) begin sel<=8'b1111_0111; {a,b,c,d,e,f,g}<=7'b1111110; end else sel<=8'b1111_1111; state<=s5; end s5: begin if(en[2]) begin sel<=8'b1111_1011; {a,b,c,d,e,f,g}<=7'b1101101; end else sel<=8'b1111_1111; state<=s6; end s6: begin if(en[1]) begin sel<=8'b1111_1101; {a,b,c,d,e,f,g}<=7'b1111110; end else sel<=8'b1111_1111; state<=s7; end s7: begin if(en[0]) begin sel<=8'b1111_1110; {a,b,c,d,e,f,g}<=7'b1111001; end else sel<=8'b1111_1111; state<=s0; end default:state<=s0; endcase end endmodule

//模块定义
module sy2(a,b,c,d,e,f,g,sel,clk,en);
//输出端口
output a,b,c,d,e,f,g;
//输出端口，8位二进制数
output [7:0]sel;
//输入端口，8位二进制数
input [7:0] en;
//输入端口，时钟信号
input clk;
//寄存器定义
reg a,b,c,d,e,f,g;
//寄存器定义，8位二进制数
reg [7:0] sel;
//时钟寄存器
reg clk_reg;
//计数器
reg [8:0] count;
//状态寄存器
reg [2:0] state;
//状态常量定义
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,
s4=3'd4,s5=3'd5,s6=3'd6,s7=3'd7;
//时钟上升沿时执行的语句
always@(posedge clk)
//计数器计数到400时，时钟反转
if(count==9'd400)
begin
clk_reg<=~clk_reg;
count<=9'd0;
end
else
count<=count+9'd1;
//时钟反转边沿时执行的语句
always@(posedge clk_reg)
begin
case(state)
s0:
begin
if(en[7])
begin
sel<=8'b0111_1111;
{a,b,c,d,e,f,g}<=7'b1101101;
end
else sel<=8'b1111_1111;
state<=s1;
end
s1:
begin
if(en[6])
begin
sel<=8'b1011_1111;
{a,b,c,d,e,f,g}<=7'b1111110;
end
else sel<=8'b1111_1111;
state<=s2;
end
s2:
begin
if(en[5])
begin
sel<=8'b1101_1111;
{a,b,c,d,e,f,g}<=7'b1111110;
end
else sel<=8'b1111_1111;
state<=s3;
end
s3:
begin
if(en[4])
begin
sel<=8'b1110_1111;
{a,b,c,d,e,f,g}<=7'b1101101;
end
else sel<=8'b1111_1111;
state<=s4;
end
s4:
begin
if(en[3])
begin
sel<=8'b1111_0111;
{a,b,c,d,e,f,g}<=7'b1111110;
end
else sel<=8'b1111_1111;
state<=s5;
end
s5:
begin
if(en[2])
begin
sel<=8'b1111_1011;
{a,b,c,d,e,f,g}<=7'b1101101;
end
else sel<=8'b1111_1111;
state<=s6;
end
s6:
begin
if(en[1])
begin
sel<=8'b1111_1101;
{a,b,c,d,e,f,g}<=7'b1111110;
end
else sel<=8'b1111_1111;
state<=s7;
end
s7:
begin
if(en[0])
begin
sel<=8'b1111_1110;
{a,b,c,d,e,f,g}<=7'b1111001;
end
else sel<=8'b1111_1111;
state<=s0;
end
default:
state<=s0;
endcase
end

//模块结束
endmodule