使用Verilog语言，完成已编极化码通过高斯信道模块和SC译码模块，并给出testbench。（信息位4，编码长度8）

下面是一个简单的Verilog代码实现已编极化码通过高斯信道模块和SC译码模块的过程，并附带testbench。

module polar_encoding(
  input [3:0] data_in,
  output reg [7:0] encoded_data
);

  reg [7:0] u;
  reg [7:0] v;
  reg [7:0] c;

  always @ (data_in) begin
    u[0] = data_in[0];
    u[1] = data_in[1];
    u[2] = data_in[2];
    u[3] = data_in[3];
    u[4] = u[0] ^ u[1];
    u[5] = u[1] ^ u[2];
    u[6] = u[2] ^ u[3];
    u[7] = u[3];
  end

  always @ (u) begin
    v[0] = u[0];
    v[1] = u[1] ^ u[0];
    v[2] = u[2] ^ u[1];
    v[3] = u[3] ^ u[2];
    v[4] = u[4] ^ u[3];
    v[5] = u[5] ^ u[4];
    v[6] = u[6] ^ u[5];
    v[7] = u[7] ^ u[6];
  end

  always @ (v) begin
    c[0] = v[0];
    c[1] = v[1];
    c[2] = v[2];
    c[3] = v[3];
    c[4] = v[4];
    c[5] = v[5];
    c[6] = v[6];
    c[7] = v[7];
  end

  assign encoded_data = c;

endmodule

module gauss_channel(
  input [7:0] encoded_data,
  output reg [7:0] received_data
);

  reg [7:0] noise;

  initial begin
    noise = $random;
  end

  always @ (encoded_data) begin
    received_data = encoded_data + noise;
  end

endmodule

module sc_decoder(
  input [7:0] received_data,
  output reg [3:0] decoded_data
);

  reg [7:0] llr;

  always @ (received_data) begin
    llr[0] = received_data[0] - received_data[1];
    llr[1] = received_data[2] - received_data[3];
    llr[2] = received_data[4] - received_data[5];
    llr[3] = received_data[6] - received_data[7];
  end

  always @ (llr) begin
    if (llr[0] > 0) begin
      decoded_data[0] = 0;
    end else begin
      decoded_data[0] = 1;
    end
    if (llr[1] > 0) begin
      decoded_data[1] = 0;
    end else begin
      decoded_data[1] = 1;
    end
    if (llr[2] > 0) begin
      decoded_data[2] = 0;
    end else begin
      decoded_data[2] = 1;
    end
    if (llr[3] > 0) begin
      decoded_data[3] = 0;
    end else begin
      decoded_data[3] = 1;
    end
  end

endmodule

module testbench();

  reg [3:0] data_in;
  reg clk;
  wire [7:0] encoded_data;
  wire [7:0] received_data;
  wire [3:0] decoded_data;

  polar_encoding pe(.data_in(data_in), .encoded_data(encoded_data));
  gauss_channel gc(.encoded_data(encoded_data), .received_data(received_data));
  sc_decoder scd(.received_data(received_data), .decoded_data(decoded_data));

  initial begin
    data_in = 4'd0;
    clk = 1'b0;
    #10;
    while (1) begin
      data_in = data_in + 1;
      #10;
      if (data_in == 4'd15) begin
        $finish;
      end
    end
  end

  always #5 clk = ~clk;

endmodule

这个testbench会对所有4位二进制数据进行测试。可以通过仿真来验证电路的正确性。