用Verilog HDL设计系统,按照(3’b000->3’ b001->3’ b011->3’b111->3’b101->3b100->3’b110->3'b010->3’b000）b010->3’b000）规律工作的计数器，对输入时钟信号进行计数。要习1、系统可以异步复位，同步使能2、用四位一体数码管对计数值以二讲制形式讲行实时、同步显示并给出测试文件代码

好的，下面是带有测试文件的Verilog HDL设计：

module counter(
  input clk, //输入时钟信号
  input rst, //异步复位信号
  input en,  //同步使能信号
  output reg [3:0] seg //四位一体数码管输出
);

reg [2:0] count; //计数器寄存器
reg [2:0] next_count; //下一个计数器值

//计数器状态转移规律
always @ (posedge clk or posedge rst) begin
  if (rst) begin
    count <= 3'b000; //复位时计数器清零
  end else if (en) begin
    count <= next_count; //使能时根据规律更新计数器值
  end
end

//根据规律生成下一个计数器值
always @ (count) begin
  case (count)
    3'b000: next_count = 3'b001;
    3'b001: next_count = 3'b011;
    3'b011: next_count = 3'b111;
    3'b111: next_count = 3'b101;
    3'b101: next_count = 3'b100;
    3'b100: next_count = 3'b110;
    3'b110: next_count = 3'b010;
    3'b010: next_count = 3'b000;
    default: next_count = 3'b000;
  endcase
end

//将计数器值转换为二进制数并输出到数码管上
always @ (count) begin
  case (count)
    3'b000: seg = 4'b0000;
    3'b001: seg = 4'b0001;
    3'b010: seg = 4'b0010;
    3'b011: seg = 4'b0011;
    3'b100: seg = 4'b0100;
    3'b101: seg = 4'b0101;
    3'b110: seg = 4'b0110;
    3'b111: seg = 4'b0111;
    default: seg = 4'b0000;
  endcase
end

endmodule

测试文件代码如下：

`timescale 1ns / 1ps

module counter_tb;

reg clk;
reg rst;
reg en;
wire [3:0] seg;

counter uut (
  .clk(clk),
  .rst(rst),
  .en(en),
  .seg(seg)
);

initial begin
  clk = 0;
  rst = 1;
  en = 0;
  #100 rst = 0;
  #100 en = 1;
end

always #5 clk = ~clk;

endmodule

该测试文件将时钟信号、复位信号和使能信号分别初始化为低电平、高电平和低电平，并在时钟信号上每5个时钟周期翻转一次。在100个时钟周期后，将复位信号置为低电平，再过100个时钟周期后，将使能信号置为高电平。

希望这个Verilog HDL设计和测试文件能够满足您的需求。