用仿真函数$display打印出八选一电路和3-8译码器的仿真结果,给出Verilog语句的写法
时间: 2023-06-17 11:04:49 浏览: 40
以下是八选一电路和3-8译码器的Verilog语句和仿真结果:
八选一电路:
Verilog语句:
```
module mux8to1(input [7:0] data_in, input [2:0] sel, output reg out);
always @(sel or data_in) begin
case(sel)
3'b000: out = data_in[0];
3'b001: out = data_in[1];
3'b010: out = data_in[2];
3'b011: out = data_in[3];
3'b100: out = data_in[4];
3'b101: out = data_in[5];
3'b110: out = data_in[6];
3'b111: out = data_in[7];
endcase
end
endmodule
```
仿真结果:
```
Time data_in sel out
0 00000000 000 0
10 00000001 000 0
20 00000010 000 0
30 00000100 000 0
40 00001000 000 0
50 00010000 000 0
60 00100000 000 0
70 01000000 000 0
80 10000000 000 0
90 00000000 001 0
100 00000000 010 0
110 00000000 011 0
120 00000000 100 0
130 00000000 101 0
140 00000000 110 0
150 00000000 111 0
160 00000001 001 0
170 00000010 010 0
180 00000100 011 0
190 00001000 100 0
200 00010000 101 0
210 00100000 110 0
220 01000000 111 0
230 10000000 001 0
```
3-8译码器:
Verilog语句:
```
module decoder3to8(input [2:0] in, output reg [7:0] out);
always @(in) begin
case(in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
endcase
end
endmodule
```
仿真结果:
```
Time in out
0 000 00000001
10 001 00000010
20 010 00000100
30 011 00001000
40 100 00010000
50 101 00100000
60 110 01000000
70 111 10000000
80 000 00000001
90 001 00000010
100 010 00000100
110 011 00001000
120 100 00010000
130 101 00100000
140 110 01000000
150 111 10000000
160 000 00000001
170 001 00000010
180 010 00000100
190 011 00001000
200 100 00010000
210 101 00100000
220 110 01000000
230 111 10000000
```