用verilog设计一个3-8译码器,要求使用case语句
时间: 2024-05-20 14:17:38 浏览: 92
verilog 编写的3-8译码程序
module decoder3to8(input [2:0] in, output reg [7:0] out);
always @(*) begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000;
endcase
end
endmodule
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