写三个FIFO用Verilog把两个FIFO从0-99和100-199写入第三个FIFO中

以下是一个简单的Verilog代码示例，用于实现三个FIFO并将两个FIFO合并为第三个FIFO：

module fifo(input clk, reset,
            input [7:0] data_in,
            input write_en, read_en,
            output [7:0] data_out);

    parameter MAX_DEPTH = 100;

    reg [7:0] memory [MAX_DEPTH-1:0];
    reg [6:0] write_ptr, read_ptr;
    reg [6:0] count;

    always @(posedge clk) begin
        if (reset) begin
            write_ptr <= 0;
            read_ptr <= 0;
            count <= 0;
        end else begin
            if (write_en && count < MAX_DEPTH) begin
                memory[write_ptr] <= data_in;
                write_ptr <= write_ptr + 1;
                count <= count + 1;
            end
            if (read_en && count > 0) begin
                data_out <= memory[read_ptr];
                read_ptr <= read_ptr + 1;
                count <= count - 1;
            end
        end
    end

endmodule

module fifo_merge(input clk, reset,
                  input [7:0] data_in_1,
                  input [7:0] data_in_2,
                  input write_en_1, read_en_1,
                  input write_en_2, read_en_2,
                  output [7:0] data_out,
                  output reg empty, full);

    parameter MAX_DEPTH = 200;

    reg [7:0] memory [MAX_DEPTH-1:0];
    reg [6:0] write_ptr_1, read_ptr_1;
    reg [6:0] write_ptr_2, read_ptr_2;
    reg [6:0] count;

    fifo fifo_1 (.clk(clk), .reset(reset),
                 .data_in(data_in_1), .write_en(write_en_1), .read_en(read_en_1),
                 .data_out(memory[write_ptr_1]));
    fifo fifo_2 (.clk(clk), .reset(reset),
                 .data_in(data_in_2), .write_en(write_en_2), .read_en(read_en_2),
                 .data_out(memory[write_ptr_2]));

    always @(posedge clk) begin
        if (reset) begin
            write_ptr_1 <= 0;
            read_ptr_1 <= 0;
            write_ptr_2 <= MAX_DEPTH/2;
            read_ptr_2 <= MAX_DEPTH/2;
            count <= 0;
            empty <= 1;
            full <= 0;
        end else begin
            if ((write_en_1 || write_en_2) && count < MAX_DEPTH) begin
                if (write_en_1) begin
                    memory[write_ptr_1] <= data_in_1;
                    write_ptr_1 <= write_ptr_1 + 1;
                end else begin
                    memory[write_ptr_2] <= data_in_2;
                    write_ptr_2 <= write_ptr_2 + 1;
                end
                count <= count + 1;
                empty <= 0;
                if (count == MAX_DEPTH) full <= 1;
            end
            if ((read_en_1 || read_en_2) && count > 0) begin
                if (read_en_1) begin
                    data_out <= memory[read_ptr_1];
                    read_ptr_1 <= read_ptr_1 + 1;
                end else begin
                    data_out <= memory[read_ptr_2];
                    read_ptr_2 <= read_ptr_2 + 1;
                end
                count <= count - 1;
                full <= 0;
                if (count == 0) empty <= 1;
            end
        end
    end

endmodule

上述代码包括两个模块：`fifo` 和 `fifo_merge`。`fifo` 模块实现了一个基本的FIFO，可以进行读、写和清空操作。`fifo_merge` 模块是最终的FIFO合并器，它将两个FIFO输入合并成一个FIFO输出。

在 `fifo_merge` 模块中，我们使用了两个 `fifo` 实例来分别处理两个输入FIFO。当写入使能信号为高电平且FIFO未满时，数据将被写入到第一个或第二个FIFO中。当读取使能信号为高电平且FIFO非空时，数据将从第一个或第二个FIFO中读取。

在整个过程中，计数器 `count` 记录FIFO中的数据数量，并且 `empty` 和 `full` 信号分别指示FIFO是否为空或已满。

最终输出的 `data_out` 信号是从合并后的FIFO中读取的数据。