用verilog写8位优先编码器的模型文件和测试文件

模型文件：

module priority_encoder(input [7:0] data, output [2:0] index);

assign index = {data[7], data[6], data[5], data[4], data[3], data[2], data[1], data[0]};

endmodule

测试文件：

module priority_encoder_test;

reg [7:0] data;
wire [2:0] index;

priority_encoder uut(
    .data(data),
    .index(index)
);

initial begin
    // Test case 1: Input all zeros
    data = 8'b00000000;
    #10;
    if (index !== 3'b000) $display("Test case 1 failed.");

    // Test case 2: Input all ones
    data = 8'b11111111;
    #10;
    if (index !== 3'b111) $display("Test case 2 failed.");

    // Test case 3: Input alternating zeros and ones
    data = 8'b10101010;
    #10;
    if (index !== 3'b101) $display("Test case 3 failed.");

    // Test case 4: Input random values
    data = 8'b01101001;
    #10;
    if (index !== 3'b100) $display("Test case 4 failed.");

    // Test case 5: Input random values
    data = 8'b11010100;
    #10;
    if (index !== 3'b110) $display("Test case 5 failed.");

    $display("All test cases passed!");
    $finish;
end

endmodule