Cypress S6J32XX系列微控制器硬件用户手册

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Table of Contents     
 
 
Traveo Family Hardware Manual Platform Part, Doc. No. 002-04854 Rev. *D 
37.  IRC ECC Error Vector Address Register (IRCn_IRQEEVA) .......................... 1333 
 Others ............................................................................................................................ 1334 
CHAPTER 23:  Time Protection ............................................................................................. 1335 
 Overview ........................................................................................................................ 1336 
 Configuration ................................................................................................................. 1337 
 Explanation of Operation ............................................................................................... 1338 
 Setting Procedure Examples ......................................................................................... 1340 
 Registers ....................................................................................................................... 1342 
1.  TPU Lock Release Register (TPU0_UNLOCK) ............................................ 1344 
2.  TPU Lock Status Register (TPU0_LST)........................................................ 1345 
3.  TPU Configuration Register (TPU0_CFG) .................................................... 1346 
4.  TPU Timer Interrupt Request Register (TPU0_TIR) ..................................... 1348 
5.  TPU Timer Status Register (TPU0_TST) ...................................................... 1349 
6.  TPU Timer Interrupt Enable Register (TPU0_TIE) ........................................ 1350 
7.  TPU Timer m Control Register 0 (TPU0_TCN0m) ........................................ 1351 
8.  TPU Timer m Control Register 1 (TPU0_TCN1m) ........................................ 1353 
9.  TPU Timer m Current Count Value Register (TPU0_TCCm) ........................ 1355 
 Others ............................................................................................................................ 1356 
CHAPTER 24:  Security ......................................................................................................... 1357 
 Overview ........................................................................................................................ 1358 
 Security Scope and Access Restriction by the Security ................................................. 1359 
1.  Security Scope .............................................................................................. 1359 
2.  Access Restriction by the Security ................................................................ 1361 
 Using and Configuring the Security ............................................................................... 1362 
1.  Set Security Setting ...................................................................................... 1363 
2.  Erasing Security Setting ................................................................................ 1364 
3.  Security Marker Definition ............................................................................. 1366 
4.  Gain access in USERMODE ......................................................................... 1373 
 Registers ....................................................................................................................... 1376 
1.  Security Status Register (TCFCFG0_SECSTAT) .......................................... 1378 
2.  Security Enable Register (TCFCFG0_SER) ................................................. 1381 
3.  Security Scope Register (TCFCFG0_SSR) .................................................. 1383 
4.  Chip Erase Enable Register (TCFCFG0_CEER) .......................................... 1385 
5.  Security Overwrite Enable Register (TCFCFG0_SOER) .............................. 1387 
6.  Sector Write Permission Overwrite Enable Register (TCFCFG0_SWPOER)   
  ...................................................................................................................... 1389 
7.  Work Flash Sector Write Permissions Register (TCFCFG0_WSWP) ........... 1391 
8.  Code Flash 0 Sector Write Permissions of the Small Sectors Register 
(TCFCFG0_C0SWP) .................................................................................... 1394 
9.  Code Flash 0 Sector Write Permissions of the Large Sectors Register 
(TCFCFG0_C1SWP) .................................................................................... 1396 
10.  Code Flash 1 Sector Write Permissions of the Large Sectors Register 
(TCFCFG0_C2SWP) .................................................................................... 1401 
11.  Code Flash 2 Sector Write Permissions of the Large Sectors Register 
(TCFCFG0_C3SWP) .................................................................................... 1406 
CHAPTER 25:  Memory Protection Unit for AXI of SHE ........................................................ 1411 
 Overview ........................................................................................................................ 1412 
 Configuration and Block Diagram .................................................................................. 1413 

  Table of Contents 
 
 
Traveo Family Hardware Manual Platform Part, Doc. No. 002-04854 Rev. *D  17 
 Operation of the MPU AXI ............................................................................................. 1414 
 Registers ....................................................................................................................... 1421 
1.  MPU AXI Control Register (MPUXSHE_CTRL0) .......................................... 1424 
2.  MPU AXI NMI Enable Register (MPUXSHE_NMIEN) ................................... 1427 
3.  MPU AXI Write Error Control Register (MPUXSHE_WERRC) ...................... 1428 
4.  MPU AXI Write Error Address Register (MPUXSHE_WERRA) .................... 1430 
5.  MPU AXI Read Error Control Register (MPUXSHE_RERRC) ...................... 1431 
6.  MPU AXI Read Error Address Register (MPUXSHE_RERRA) ..................... 1433 
7.  MPU AXI Region Control Registers (MPUXSHE_CTRL1~8) ........................ 1434 
8.  MPU AXI Start Address Registers (MPUXSHE_SADDR1~8) ....................... 1436 
9.  MPU AXI End Address Registers (MPUXSHE_EADDR1~8) ........................ 1437 
10.  MPU AXI Unlock Register (MPUXSHE_UNLOCK) ....................................... 1438 
11.  MPU AXI Module ID Register (MPUXSHE_MID) .......................................... 1439 
 Notes on Using MPU AXI .............................................................................................. 1440 
CHAPTER 26:  Secure Hardware Extension (SHE) .............................................................. 1443 
 Outline of the Secure Hardware Extension (SHE) Module ............................................ 1444 
 Secure Hardware Extension Registers .......................................................................... 1446 
1.  Configuration Registers for the Command Interface ..................................... 1453 
2.  Status Registers for the Command Interface ................................................ 1459 
3.  Interrupt Registers for Command Interface ................................................... 1468 
4.  Configuration Registers for the Data Interface .............................................. 1475 
5.  Status Registers for Data Interface ............................................................... 1490 
6.  Data Transfer Registers ................................................................................ 1503 
 Operation of the Secure Hardware Extension ............................................................... 1507 
1.  Operation of the Command Interface ............................................................ 1507 
2.  Operation of the Data Interface ..................................................................... 1521 
3.  Operation of the FIFO Unit ............................................................................ 1526 
 Notes on Using SHE ...................................................................................................... 1530 
1.  General Notes on Using SHE ....................................................................... 1530 
 Enhanced Secure Hardware Extension ......................................................................... 1536 
1.  Additional Generate Purpose Keys ............................................................... 1536 
2.  Additional Verify Only Flag ............................................................................ 1537 
3.  Additional User-accessible Functions ........................................................... 1538 
 References .................................................................................................................... 1541 
CHAPTER 27:  DMA Controller ............................................................................................. 1543 
 Overview ........................................................................................................................ 1544 
 Configuration ................................................................................................................. 1545 
 Operational Description ................................................................................................. 1547 
1.  DMA Channels .............................................................................................. 1549 
2.  DMA Client Matrix ......................................................................................... 1559 
3.  DMA Arbiter ................................................................................................... 1561 
4.  DMA AHB Slave Interface ............................................................................. 1564 
5.  Additional Information ................................................................................... 1565 
 Registers ....................................................................................................................... 1569 
1.  DMA Controller Global Configuration Register (DMAi_R) ............................. 1571 
2.  DMA Controller Global Completion Interrupt 1 Register (DMAi_DIRQ1) ...... 1574 
3.  DMA Controller Global Completion Interrupt 2 Register (DMAi_DIRQ2) ...... 1575 
4.  DMA Controller Global Error Interrupt 1 Register (DMAi_EDIRQ1) .............. 1576 

Table of Contents     
 
 
18  Traveo Family Hardware Manual Platform Part, Doc. No. 002-04854 Rev. *D 
4.5.  DMA Controller Global Error Interrupt 2 Register (DMAi_EDIRQ2) .............. 1577 
4.6.  DMA Controller ID Register (DMAi_ID) ......................................................... 1578 
4.7.  DMA Controller Channel Configuration A Register Channel 'n' (DMAi_An)... 1579 
4.8.  DMA Controller Channel Configuration B Register Channel 'n' (DMAi_Bn)   
  ...................................................................................................................... 1582 
4.9.  DMA Controller Channel Configuration Source Address Register Channel 'n' 
(DMAi_SAn) .................................................................................................. 1586 
4.10.  DMA Controller Channel Configuration Destination Address Register Channel 
'n' (DMAi_DAn) ............................................................................................. 1587 
4.11.  DMA Controller Channel Configuration C Register Channel 'n' (DMAi_Cn)   
  ...................................................................................................................... 1588 
4.12.  DMA Controller Channel Configuration D Register Channel 'n' (DMAi_Dn)   
  ...................................................................................................................... 1589 
4.13.  DMA Controller Channel Configuration E Register Channel 'n' (DMAi_En)   
  ...................................................................................................................... 1592 
4.14.  DMA Controller Channel Configuration Source Address Shadow Register 
Channel 'n' (DMAi_SASHDWn) .................................................................... 1593 
4.15.  DMA Controller Channel Configuration Destination Address Shadow Register 
Channel 'n' (DMAi_DASHDWn) .................................................................... 1594 
4.16.  DMA Controller Client Matrix Internal Client Interface Configuration Register 
'm' (DMAi_CMICICm) .................................................................................... 1595 
4.17.  DMA Controller Client Matrix Channel Interface Configuration Register 'n' 
(DMAi_CMCHICn) ........................................................................................ 1597 
5.  Additional Information .................................................................................................... 1599 
CHAPTER 28:  DMA COMPLEX SUBSYSTEM .................................................................... 1601 
1.  Overview ........................................................................................................................ 1602 
2.  Configuration and Block Diagram .................................................................................. 1603 
3.  Operation of the DMA COMPLEX SUBSYSTEM .......................................................... 1605 
3.1.  Additional Status Registers ........................................................................... 1606 
3.2.  CMCHIC Reloading ...................................................................................... 1607 
3.3.  Reload Timer in DMA Additional Control ....................................................... 1608 
4.  Registers ....................................................................................................................... 1613 
4.1.  DMA Additional Control Additional Status Register 0 (DMAAn_ASR0) ......... 1617 
4.2.  DMA Additional Control Additional Status Register 1 (DMAAn_ASR1) ......... 1618 
4.3.  DMA Additional Control Additional Status Register 2 (DMAAn_ASR2) ......... 1619 
4.4.  DMA Additional Control Additional Status Register 3 (DMAAn_ASR3) ......... 1620 
4.5.  DMA Additional Control Additional Status Register i (DMAAn_ASRi) (i=4 to 
19)................................................................................................................. 1621 
4.6.  DMA Additional Control CMCHIC Reload Data Bank Register i 
(DMAAn_CMCHICRDBi) (i=0 to 7) ............................................................... 1622 
4.7.  DMA Additional Control Reload Timer Trigger Select Register 
(DMAAn_RTTSR) ......................................................................................... 1623 
4.8.  DMA Additional Control Reload Timer Synchronous Software Start Register 
(DMAAn_RTSSSR) ....................................................................................... 1625 
5.  Overview in DMA COMPLEX SUBSYSTEM ................................................................. 1626 
6.  Configuration and Block Diagram in DMA COMPLEX SUBSYSTEM ............................ 1627 
7.  Operation of the 32-Bit Reload Timer in DMA COMPLEX SUBSYSTEM ...................... 1628 
 

  Table of Contents 
 
 
Traveo Family Hardware Manual Platform Part, Doc. No. 002-04854 Rev. *D  19 
1.  Internal Clock and External Event Counter Operations of 32-Bit Reload Timer 
  ...................................................................................................................... 1629 
2.  Underflow Operation of 32-Bit Reload Timer ................................................ 1631 
3.  Output Functions of 32-Bit Reload Timer ...................................................... 1633 
4.  Counter Operation State ............................................................................... 1634 
5.  DMA Operation ............................................................................................. 1635 
 Registers in DMA COMPLEX SUBSYSTEM ................................................................. 1636 
1.  DMA Configuration Register (DMAAn_RLTm_DMACFG) ............................. 1637 
2.  Timer Control Status Register (DMAAn_RLTm_TMCSR) ............................. 1638 
3.  32-Bit Reload Register (DMAAn_RLTm_TMRLR) ........................................ 1642 
4.  32-Bit Timer Register (DMAAn_RLTm_TMR) ............................................... 1643 
CHAPTER 29:  MPU16 AHB ................................................................................................. 1645 
 Outline of the MPU16 AHB ............................................................................................ 1646 
 Configuration and Diagram ............................................................................................ 1647 
 MPU16 AHB Registers .................................................................................................. 1648 
1.  MPU16 AHB Control Register (MPUHn_CTRL0) .......................................... 1652 
2.  MPU16 AHB NMI Enable Register (MPUHn_NMIEN) .................................. 1654 
3.  MPU16 AHB Memory Error Control Register (MPUHn_MERRC) ................. 1655 
4.  MPU AHB Memory Error Address Register (MPUHn_MERRA) .................... 1656 
5.  MPU16 AHB Region Control Registers (MPUHn_CTRL1 to 16) ................... 1657 
6.  MPU16 AHB Start Address Registers (MPUHn_SADDR1 to 16) .................. 1659 
7.  MPU16 AHB End Address Registers (MPUHn_EADDR1 to 16) ................... 1660 
8.  MPU16 AHB Unlock Register (MPUHn_UNLOCK) ....................................... 1661 
9.  MPU16 AHB Module ID Register (MPUHn_MID) .......................................... 1662 
 Operation of the MPU16 AHB ........................................................................................ 1663 
CHAPTER 30:  CAN FD Controller(MCAN3.0.1) ................................................................... 1667 
 Overview ........................................................................................................................ 1668 
 Configuration ................................................................................................................. 1669 
1.  Block Diagram .............................................................................................. 1669 
2.  Dual Clock Sources ...................................................................................... 1670 
3.  Dual Interrupt Lines ...................................................................................... 1670 
 Explanation of Operations ............................................................................................. 1671 
1.  Operating Modes .......................................................................................... 1671 
2.  Timestamp Generation ................................................................................. 1682 
3.  Timeout Counter ........................................................................................... 1682 
4.  Rx Handling .................................................................................................. 1683 
5.  Tx Handling ................................................................................................... 1694 
6.  FIFO Acknowledge Handling ........................................................................ 1700 
7.  Configuring the CAN Bit Timing .................................................................... 1700 
 Setup Procedure Examples ........................................................................................... 1704 
1.  Configuration of CAN Bus ............................................................................. 1706 
2.  Configuration of Message RAM .................................................................... 1707 
3.  Configuration of Error Monitor ....................................................................... 1712 
4.  Configuration of Interrupt .............................................................................. 1713 
5.  Control of Communication ............................................................................ 1714 
6.  Interrupt Handling Operation ......................................................................... 1717 

Table of Contents     
 
 
Traveo Family Hardware Manual Platform Part, Doc. No. 002-04854 Rev. *D 
 Registers ....................................................................................................................... 1727 
1.  Core Release Register (MCG_CANFDx_CREL, CPG_CANFDx_CREL) ..... 1736 
2.  Endian Register (MCG_CANFDx_ENDN, CPG_CANFDx_ENDN)............... 1738 
3.  Fast Bit Timing & Prescaler Register (MCG_CANFDx_FBTP, 
CPG_CANFDx_FBTP) .................................................................................. 1739 
4.  Test Register (MCG_CANFDx_TEST, CPG_CANFDx_TEST) ..................... 1742 
5.  RAM Watchdog (MCG_CANFDx_RWD, CPG_CANFDx_RWD) .................. 1744 
6.  CC Control Register (MCG_CANFDx_CCCR, CPG_CANFDx_CCCR)........ 1746 
7.  Bit Timing & Prescaler Register (MCG_CANFDx_BTP, CPG_CANFDx_BTP)   
  ...................................................................................................................... 1750 
8.  Timestamp Counter Configuration (MCG_CANFDx_TSCC, 
CPG_CANFDx_TSCC) ................................................................................. 1753 
9.  Timestamp Counter Value (MCG_CANFDx_TSCV, CPG_CANFDx_TSCV)   
  ...................................................................................................................... 1755 
10.  Timeout Counter Configuration (MCG_CANFDx_TOCC, 
CPG_CANFDx_TOCC) ................................................................................. 1756 
11.  Timeout Counter Value (MCG_CANFDx_TOCV, CPG_CANFDx_TOCV) .... 1758 
12.  Error Counter Register (MCG_CANFDx_ECR, CPG_CANFDx_ECR) ......... 1760 
13.  Protocol Status Register (MCG_CANFDx_PSR, CPG_CANFDx_PSR) ....... 1762 
14.  Interrupt Register (MCG_CANFDx_IR, CPG_CANFDx_IR) ......................... 1766 
15.  Interrupt Enable (MCG_CANFDx_IE, CPG_CANFDx_IE) ............................ 1772 
16.  Interrupt Line Select (MCG_CANFDx_ILS, CPG_CANFDx_ILS) ................. 1774 
17.  Interrupt Line Enable (MCG_CANFDx_ILE, CPG_CANFDx_ILE) ................ 1776 
18.  Global Filter Configuration (MCG_CANFDx_GFC, CPG_CANFDx_GFC).... 1777 
19.  Standard ID Filter Configuration (MCG_CANFDx_SIDFC, 
CPG_CANFDx_SIDFC) ................................................................................ 1779 
20.  Extended ID Filter Configuration (MCG_CANFDx_XIDFC, 
CPG_CANFDx_XIDFC) ................................................................................ 1781 
21.  Extended ID AND Mask (MCG_CANFDx_XIDAM, CPG_CANFDx_XIDAM)   
  ...................................................................................................................... 1783 
22.  High Priority Message Status (MCG_CANFDx_HPMS, 
CPG_CANFDx_HPMS) ................................................................................ 1784 
23.  New Data 1 (MCG_CANFDx_NDAT1, CPG_CANFDx_NDAT1) ................... 1786 
24.  New Data 2 (MCG_CANFDx_NDAT 2, CPG_CANFDx_NDAT 2) ................. 1787 
25.  Rx FIFO 0 Configuration (MCG_CANFDx_RXF0C, CPG_CANFDx_RXF0C)   
  ...................................................................................................................... 1788 
26.  Rx FIFO 0 Status (MCG_CANFDx_RXF0S, CPG_CANFDx_RXF0S).......... 1790 
27.  Rx FIFO 0 Acknowledge (MCG_CANFDx_RXF0A, CPG_CANFDx_RXF0A)   
  ...................................................................................................................... 1792 
28.  Rx Buffer Configuration (MCG_CANFDx_RXBC, CPG_CANFDx_RXBC) ... 1793 
29.  Rx FIFO 1 Configuration (MCG_CANFDx_RXF1C, CPG_CANFDx_RXF1C)   
  ...................................................................................................................... 1794 
30.  Rx FIFO 1 Status (MCG_CANFDx_RXF1S, CPG_CANFDx_RXF1S).......... 1796 
31.  Rx FIFO 1 Acknowledge (MCG_CANFDx_RXF1A, CPG_CANFDx_RXF1A)   
  ...................................................................................................................... 1798 
32.  Rx Buffer/FIFO Element Size Configuration (MCG_CANFDx_RXESC, 
CPG_CANFDx_RXESC) .............................................................................. 1799 
33.  Tx Buffer Configuration (MCG_CANFDx_TXBC, CPG_CANFDx_TXBC) .... 1801 