2013年IEEE 1149.1标准：测试接口与边界扫描架构详解

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IEEE Std 1149.1-2013，正式名称为《IEEE标准测试访问端口与边界扫描架构》，是由IEEE Test Technology Standards Committee（IEEE TTS Committee）发起并维护的一份官方文档。该标准于2013年5月13日发布，是对2001年版本IEEE Std 1149.1的一个修订。这份标准定义了测试访问端口（Test Access Port, TAP）和边界扫描（Boundary-Scan）技术在集成电路设计和制造中的应用，主要目的是为了协助对集成电路以及组装后的印刷电路板进行测试、维护和支持。标准涵盖了以下几个关键知识点： 1. **测试访问端口（TAP）**：TAP是集成电路中专用于测试目的的接口，允许测试工具通过这个接口与电路内部的逻辑单元进行通信，执行诊断和修复操作。TAP的设计包括一组预定义的功能，如读取、写入寄存器，以及控制信号，使得调试和故障检测成为可能。 2. **边界扫描**：这是一种在集成电路设计中实现的故障隔离方法，允许测试人员通过专用的数据线（通常在芯片边缘）逐个检查和修改单个或多个组件的状态，而无需物理访问整个电路板。这大大提高了测试的灵活性和效率。 3. **标准体系结构**：IEEE Std 1149.1提供了一套统一的接口规范和操作流程，确保不同制造商生产的集成电路之间的兼容性，便于集成到各种测试系统中。 4. **应用范围**：标准适用于各种电子设备，包括计算机、通信设备、消费电子产品等，对于工业界来说，它在电子产品生命周期管理中起着至关重要的作用，从设计、制造到维修阶段都能提供支持。 5. **授权与限制**：IEEE Std 1149.1-2013的使用受到特定条件的限制，例如只能由INSTITUTE OF COMPUTING TECHNOLOGY CAS在2013年11月22日下载自IEEE Explore平台，并且存在使用限制。 IEEE Std 1149.1-2013是电子行业中测试和调试领域的重要参考标准，对于设计工程师、测试工程师、硬件维护人员以及设备制造商来说，理解和遵循这一标准对于确保产品质量和提升生产效率至关重要。

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xiv

Annex B (normative) Boundary Scan Description Language (BSDL) ....................................................... 189

B.1 General information ......................................................................................................................... 189

B.1.1 Document outline ................................................................................................................. 189

B.1.2 Conventions ......................................................................................................................... 189

B.1.3 BSDL history ....................................................................................................................... 189

B.2 Purpose of BSDL ........................................................................................................................ 190

B.3 Scope of BSDL ........................................................................................................................... 190

B.4 Relationship of BSDL to VHDL ................................................................................................ 191

B.4.1 Specifications ....................................................................................................................... 191

B.5 Lexical elements of BSDL .......................................................................................................... 192

B.5.1 Character set ........................................................................................................................ 192

B.5.2 BSDL reserved words .......................................................................................................... 193

B.5.3 VHDL reserved and predefined words ................................................................................ 194

B.5.4 Identifiers ............................................................................................................................. 195

B.5.5 Numeric literals ................................................................................................................... 196

B.5.6 Strings .................................................................................................................................. 197

B.5.7 Information tag .................................................................................................................... 198

B.5.8 Comments ............................................................................................................................ 199

B.6 Syntax definition ......................................................................................................................... 199

B.6.1 BNF conventions ................................................................................................................. 199

B.6.2 Commonly used syntactic elements ..................................................................................... 200

B.7 Components of a BSDL description ........................................................................................... 202

B.7.1 Specifications ....................................................................................................................... 202

B.7.2 Description ........................................................................................................................... 203

B.8 Entity description ........................................................................................................................ 203

B.8.1 Overall syntax of the entity description ............................................................................... 203

B.8.2 Generic parameter statement ................................................................................................ 204

B.8.3 Logical port description statement ....................................................................................... 205

B.8.4 Standard use statement ......................................................................................................... 208

B.8.5 Use statement ....................................................................................................................... 211

B.8.6 Component conformance statement ..................................................................................... 212

B.8.7 Device package pin mappings ............................................................................................. 213

B.8.8 Grouped port identification .................................................................................................. 216

B.8.9 Scan port identification ........................................................................................................ 219

B.8.10 Compliance-enable description ............................................................................................ 220

B.8.11 Instruction register description ............................................................................................ 221

B.8.12 Optional device register description .................................................................................... 224

B.8.13 Register access description .................................................................................................. 227

B.8.14 Boundary-scan register description ...................................................................................... 229

B.8.15 RUNBIST description .......................................................................................................... 245

B.8.16 INTEST description ............................................................................................................. 247

B.8.17 System clock requirements attribute .................................................................................... 249

B.8.18 Register mnemonics description .......................................................................................... 250

B.8.19 Register fields description ................................................................................................... 254

B.8.20 Register field assignment description .................................................................................. 261

B.8.21 Register assembly description .............................................................................................. 271

B.8.22 Register constraint description ............................................................................................. 288

B.8.23 Register and power port association attributes .................................................................... 291

B.8.24 User extensions to BSDL ..................................................................................................... 295

B.8.25 Design warning .................................................................................................................... 297

B.9 Standard BSDL Package STD_1149_1_2013 ............................................................................ 298

B.10 User-supplied BSDL packages ............................................................................................... 302

B.10.1 Specifications ....................................................................................................................... 302

B.10.2 Description ........................................................................................................................... 306

B.10.3 Examples ............................................................................................................................. 307

Authorized licensed use limited to: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Downloaded on November 22,2013 at 02:28:04 UTC from IEEE Xplore. Restrictions apply.

B.11 BSDL example applications ................................................................................................... 308

B.11.1 Typical application of BSDL ............................................................................................... 308

B.11.2 Boundary-scan register description ...................................................................................... 311

B.12 1990 version of BSDL ............................................................................................................ 315

B.12.1 1990 Standard VHDL Package STD_1149_1_1990 ............................................................ 316

B.12.2 Typical application of BSDL, 1990 version ........................................................................ 319

B.12.3 Obsolete syntax .................................................................................................................... 320

B.12.4 Miscellaneous points on 1990 version ................................................................................. 321

B.13 1994 version of BSDL ............................................................................................................ 321

B.13.1 Standard VHDL Package STD_1149_1_1994 .................................................................... 321

B.14 2001 version of BSDL ............................................................................................................ 325

B.14.1 Standard VHDL Package STD_1149_1_2001 .................................................................... 325

Annex C (normative) Procedural Description Language (PDL) ................................................................. 329

C.1 General information ......................................................................................................................... 329

C.1.1 Purpose ....................................................................................................................................... 329

C.1.2 Dependence on Tool Command Language (Tcl) ....................................................................... 330

C.1.3 Dependence on Boundary Scan Description Language (BSDL)................................................ 330

C.2 PDL concepts and use model ........................................................................................................... 330

C.2.1 Use model introduction .............................................................................................................. 330

C.2.2 PDL levels .................................................................................................................................. 332

C.2.3 PDL procedures ......................................................................................................................... 333

C.2.4 Read and write with capture-shift-update sequence ................................................................... 334

C.2.5 Register state definition ............................................................................................................. 334

C.2.6 Level-0 PDL commands ............................................................................................................ 336

C.2.7 Specification of names and values ............................................................................................. 339

C.2.8 Retargeting ................................................................................................................................. 340

C.2.9 Simple PDL Example ................................................................................................................. 341

C.3 PDL Level 0 command reference .................................................................................................... 343

C.3.1 Understanding a PDL “string” ................................................................................................... 343

C.3.2 BNF conventions ....................................................................................................................... 344

C.3.3 PDL lexical elements and common syntax ................................................................................ 345

C.3.4 PDL File ..................................................................................................................................... 350

C.3.5 Procedure definition commands ................................................................................................. 351

C.3.6 Test setup commands ................................................................................................................. 356

C.3.7 Test execution commands .......................................................................................................... 360

C.3.8 Flow-control commands ............................................................................................................ 367

C.3.9 Optimization commands ............................................................................................................ 374

C.3.10 Miscellaneous commands ........................................................................................................ 378

C.3.11 Low-level commands ............................................................................................................... 379

C.4 PDL Level 1 command reference .................................................................................................... 382

C.4.1 Level-1 PDL operation ............................................................................................................... 383

C.4.2 iGet command ............................................................................................................................ 383

C.4.3 iGetStatus command .................................................................................................................. 388

C.5 Example BSDL and PDL for the use model .................................................................................... 388

C.5.1 BSDL Packages for IP ............................................................................................................... 389

C.5.2 BSDL files for components ........................................................................................................ 390

C.5.3 PDL files supplied by IP supplier .............................................................................................. 393

C.5.4 PDL files supplied by component supplier ................................................................................ 394

C.5.5 PDL files coded by test engineer ............................................................................................... 395

Annex D (informative) Integrated examples of BSDL and PDL ................................................................ 398

D.1 Initialization example structure and procedures .............................................................................. 398

D.1.1 Initialization example using register description attributes ........................................................ 398

D.1.2 Example PDL for INIT example ................................................................................................ 405

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xvii

Figures

Figure 1-1—Boundary-scan register cell ....................................................................................................................... 3

Figure 1-2—Boundary-scannable board design ............................................................................................................ 4

Figure 1-3—Logic symbology used in this standard ..................................................................................................... 6

Figure 4-1—Serial connection using one TMS signal ................................................................................................. 18

Figure 7-2—Instruction register with decoder between shift and update stages. ........................................................ 49

Figure 8-1—Simplified view of the boundary-scan register ....................................................................................... 55

Figure 8-2—Example boundary-scan register cell design ........................................................................................... 56

Figure 8-3—Figure used to illustrate boundary-scan instructions ............................................................................... 56

Figure 8-4—Data flow for the SAMPLE instruction ................................................................................................... 58

Figure 8-5—Data flow for the PRELOAD instruction ................................................................................................. 60

Figure 8-6—Data flow for the EXTEST instruction .................................................................................................... 62

Figure 8-7—Data flow for the INTEST instruction ..................................................................................................... 64

Figure 8-8—Control of applied system clock during INTEST..................................................................................... 65

Figure 8-9—Use of TCK as clock for on-chip system logic during INTEST .............................................................. 65

Figure 8-10—Use of the HIGHZ instruction ............................................................................................................... 75

Figure 8-11—Provision of HIGHZ at a two-state pin.................................................................................................. 76

Figure 8-12—Boundary-scan register control cell with a reset on the update flip-flop R2 ......................................... 87

Figure 9-1—Implementation of the group of test data registers .................................................................................. 92

Figure 9-2—Construction of multiple test data registers from shared circuitry .......................................................... 96

Figure 9-3—Gated-clock boundary-scan register gating ............................................................................................. 97

Figure 9-4—Test data register control gating .............................................................................................................. 97

Figure 9-5—Capture-update TDR cell using gated clocks .......................................................................................... 98

Figure 9-6—Capture-update TDR cell with nongated clock and optional reset ........................................................ 100

Figure 9-7—Update TDR cell without capture and with nongated clock and optional reset .................................... 101

Figure 9-8—Capture TDR cell with nongated clock and without update stage ........................................................ 102

Figure 9-9—Shift-only TDR cell with nongated clock and without update stage. .................................................... 102

Figure 9-10—Self-monitoring TDR cell with update stage and nongated clocks ..................................................... 104

Figure 9-11—Self-resetting and self-monitoring TDR cell with nongated clocks .................................................... 105

Figure 9-12—Timing of a self-resetting and self-monitoring TDR cell at Update-DR ............................................. 106

Figure 9-13—Example design containing two optional test data registers ................................................................ 107

Figure 9-14—Scan control of excludable test data register segments ....................................................................... 112

Figure 9-15—Scan control of excludable test data register segments with domain control ...................................... 113

Figure 9-16—Domain POR reset of nested segment-select fields ............................................................................. 114

Figure 9-17—Hierarchical reset of nested segment-select fields .............................................................................. 114

Figure 9-18—Selectable segments and selection field .............................................................................................. 115

Figure 9-19—Example segment-select or selection-field cell with ungated clocks .................................................. 115

Figure 10-1—Bypass register gated-clock implementation ....................................................................................... 116

Figure 11-1—Component without boundary scan ..................................................................................................... 119

Figure 11-2—Input connections ................................................................................................................................ 120

Figure 11-3—Connection of an observe-only boundary-scan register cell ............................................................... 121

Figure 11-4—Insertion of a control-and-observe boundary-scan register cell .......................................................... 121

Figure 11-5—Conceptual view of a control-and-observe boundary-scan register cell .............................................. 122

Figure 11-6—Boundary-scan shift-register design .................................................................................................... 124

Figure 11-7—Component that contains analog circuitry ........................................................................................... 126

Figure 11-8—Placement of boundary-scan register cells .......................................................................................... 128

Figure 11-9—Component with differential inputs and outputs ................................................................................. 129

Figure 11-10—Conceptual schematic of redundant observe-only cells on differential pins ..................................... 130

Figure 11-11—Provision of a boundary-scan register cell at a system input ............................................................ 131

Figure 11-12—Provision of multiple boundary-scan register cells at one input ....................................................... 132

Figure 11-13—Noninversion of data between pin and TDO ..................................................................................... 134

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Figure 11-14—Noninversion of data between TDI and the system logic.................................................................. 134

Figure 11-15—Input cell with parallel output register [BC_2] ................................................................................. 136

Figure 11-16—Input cell without parallel output register [BC_3] ............................................................................ 136

Figure 11-17—Cell that forces the system logic input to 1 during EXTEST [BC_4] ................................................ 137

Figure 11-18—Observe-only input cell without control [BC_4] ............................................................................... 137

Figure 11-19—Input cell that supports all instructions [BC_1]................................................................................. 138

Figure 11-20—Provision of a boundary-scan register cell at a digital system output pin ......................................... 139

Figure 11-21—Provision of boundary-scan register cells at system logic outputs .................................................... 140

Figure 11-22—Provision of cells when one output Is used both as control and data ................................................ 140

Figure 11-23—Noninversion of data between the system logic and TDO ................................................................ 142

Figure 11-24—Noninversion of data between TDI and a system output pin ............................................................ 143

Figure 11-25—Noninversion of control signal values between the system logic and TDO ...................................... 144

Figure 11-26—Control of multiple three-state outputs from one signal .................................................................... 145

Figure 11-27—Testing board-level bus lines ............................................................................................................ 146

Figure 11-28—Testing external logic via the boundary-scan register ....................................................................... 147

Figure 11-29—Primitive noncompliant output cell design with potential problems ................................................. 147

Figure 11-30—Circuit illustrating potential boundary-scan test problem ................................................................. 148

Figure 11-31—Output cell that supports all instructions [BC_1] .............................................................................. 149

Figure 11-32—Output cell that does not support INTEST [BC_2] ............................................................................ 149

Figure 11-33—Self-monitoring output cell that supports INTEST [BC_9] ............................................................... 151

Figure 11-34—Self-monitoring output cell that does not support INTEST [BC_10] ................................................ 151

Figure 11-35—Boundary-scan register cells at a three-state output—Example 1 [BC_1, control and data] ............ 152

Figure 11-36—Boundary-scan register cells at a three-state output—Example 2 [BC_2, control and data] ............ 153

Figure 11-37—Boundary-scan register cells at a bidirectional pin—Example 1 [BC_1, control] ............................ 155

Figure 11-38—Boundary-scan register cells at a bidirectional pin—Example 2 [BC_2 control; BC_7 data] .......... 156

Figure 11-39—Deprecated boundary-scan register cells at a bidirectional pin [BC_2 control; BC_6 data] ............. 158

Figure 11-40—Boundary-scan register cells at an open-collector bidirectional pin [BC_4, input; BC_2, output] ... 159

Figure 11-41—Boundary-scan register cell at an open-collector bidirectional pin [BC_8] ...................................... 160

Figure 11-42—Boundary-scan register cells for use at a bidirectional pin where INTEST is not provided

[BC_2, control; BC_8, data] ............................................................................................................. 161

Figure 11-43—Cell that should not be included in the boundary-scan register ......................................................... 163

Figure 11-44—Input pins used only to control output pins—Case A ....................................................................... 164

Figure 11-45—Input pins used only to control output pins—Case B ........................................................................ 164

Figure 11-46—Noncompliant use of a single cell for output control and data .......................................................... 165

Figure 11-47—Boundary-scan register cells at a three-state pin where output control is from a system pin

[BC_5, control; BC_1, data] ............................................................................................................. 165

Figure 12-1—Structure of the device identification code .......................................................................................... 166

Figure 12-2—Device identification register gated-clock cell design......................................................................... 167

Figure 16-1—Example TMP status register (nongated clocks) ................................................................................. 177

Figure 17-1—Reset selection register overview ........................................................................................................ 178

Figure 17-2—Minimal reset selection register example ............................................................................................ 181

Figure 18-1—Measuring setup and hold timing ........................................................................................................ 187

Figure 18-2—Measuring propagation delay .............................................................................................................. 187

Figure B-1—Components of a BSDL description ..................................................................................................... 202

Figure B-2—Example use of nonboundary-scan port-types ...................................................................................... 208

Figure B-3—Example of unconnected pin types ....................................................................................................... 216

Figure B-4—Cell design corresponding to Figure 11-19 and Figure 11-31 .............................................................. 230

Figure B-5—Symbolic representation of a boundary-scan register cell .................................................................... 230

Figure B-6—Symbolic representation of a boundary-scan register cell without an update stage ............................. 231

Figure B-7—Cell on an input, which pulls to a logic 1 ............................................................................................. 243

Figure B-8—Illustration of use of <input spec> for an IC ........................................................................................ 243

Figure B-9—Illustration of use of fault detection boundary cells for an IC .............................................................. 244

Figure B-10—Simple local reset structure ................................................................................................................ 270

Figure B-11—Simple selectable register segment structure ...................................................................................... 280

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